-
Hello,
There seems to be an issue with printf formatting properties. I compiled a test program using the xPack gcc binaries:
```
#include "stdio.h"
int main()
{
int x;
for(x=0; x
-
Dear all,
I am unable to build the the rocket chip tool.
Following the read me fail has left me lot of errors and unable to build it (./build.sh just gives errors).
I am using Ubuntu 18.04 64-bit i…
pa1ly updated
4 years ago
-
Hi,
when i make -j4 run-bmark-tests-debug to dump VCD waveforms, it got stucked for dozen hours as follow:
make[1]: Leaving directory `/cm/freedom/rocket-chip/emulator/generated-src-debug/freechip…
-
template: riscv/qemu-sifive-u
qemu: 4.1.0
gcc:
```
$ riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (SiFive GCC 8.2.0-2019.05.3) 8.2.0
```
```
$qemu-system-riscv32 -nographic -m…
-
```
root@5c4c9da5f014:/# /bin/bash /start.sh
/bin/bash: /start.sh: No such file or directory
```
```
uname -a
Linux 5c4c9da5f014 5.0.0-23-generic #24~18.04.1-Ubuntu SMP Mon Jul 29 16:12:28 UTC 2…
-
Hi,
I'm currently working on a project with the rocket core. We're trying to run some come code bare-metal and doing simulations using the VLSI flow. My question is, how are the programs loaded into…
-
I followed every steps mentioned in https://github.com/esperantotech/boom-template until this error.
I succeeded in doing "make" in versim and got the executable file "simulator-boom.system-BoomConfi…
-
Hi,
Basicaly i was trying to strip down the CSR requirements of openSBI to make a softcore smaller/faster, and hit the following :
https://github.com/riscv/opensbi/blob/e5a7f556ce22984128bed0a3…
-
Renode currently allows any CSR to be read or written regardless of the privilege level. This means that it's possible for any User mode process to simply rewrite its SATP register and give itself fu…
-
Show kata-collect-data.sh details
# Meta details
Running `kata-collect-data.sh` version `1.12.0 (commit )` at `2020-12-10.22:28:59.643485993+0100`.
---
Runtime is `/usr/bin/kata-runtim…