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Renode currently allows any CSR to be read or written regardless of the privilege level. This means that it's possible for any User mode process to simply rewrite its SATP register and give itself fu…
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Hello,everyone!
I have already build the C simulator that is capable of VCD waveform generation by typing "make debug",and there was no error.
Then I run "make -jN run-asm-tests-debug",the termina…
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Related to comments in PR https://github.com/litex-hub/litex-boards/pull/31#issuecomment-573301387
The performance of the ECP5 Hackaday Badge with 32MB SDRAM is "painfully" slow.
@mithro suggest…
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from tutorial: [HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode](https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode#boot-linux-via-tftp)
I am trying the sectio…
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I run "make debug" in the verisim folder successfully, but then when I run "make run-bmark-tests-debug" I get:
cd /home/hwacha-template/verisim && /home/hwacha-template/verisim/simulator-freechips.…
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I am running QEMU emulator version 3.1.50 (qemu-3.1.50.201903180749.1d023a5-1.fc29), QEMU commit 1d023a5.
I am using master of OpenSBI, I get the following:
```
qemu-system-riscv64: plic: invalid…
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I guess this is probably more of question than a bug report so I hope you don't mind me opening an issue for this. While running OpenSBI with a custom riscv simulator I noticed that some of my simulat…
nmeum updated
5 years ago
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I found a case where Verilator's simulation is incorrect. The bug manifests when a particular circuit uses a wire's value three times, but not if it is only used twice.
The attached [cse-bug.tar.g…
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Good day!
Order and conditions
1. Adding new config WithJtagDTM in boom_configs.scala
`
class jtagMegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBigCore…