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Hi, I had new a buffer by `cl::Buffer buffer0(mContext, CL_MEM_READ_WRITE, size=4G, data=void, &err))`, then try to write buffer with `mQueue.enqueueWriteBuffer(mBuf_tw, blocking_write, 0, size=2304MB…
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你好,请问这个和zynqmp_cam_isp_demo差别仅仅是平台不同吗? ISP算法是一样的吧?
另外请教下zynqmp这个项目可以完美移植到ZCU102(XCZU9EG)上吗?
谢谢~
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Hi, the main problem is that when Im trying to compile the quantized xmodel with vai_c_xir for kv260 im getting this error:
![image](https://github.com/Xilinx/Vitis-AI/assets/148991235/5084a22b-5ae…
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Hi, Sir;
May I get an FPGA board/Xilink from your support to verify the code in FPGA/Xlink Board?
Or I could upload your code into the Lattice FPGA board such as model No. is LIFCL-40-VIP-SI-PC…
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XRT sometimes install a gcc version other than the system default. When this version is higher than the system default version, libstdc++ will not be available to Clang. This causes tapacc and tapa-cp…
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When I reproduce [cifar10_ddp](https://github.com/Xilinx/Vitis-AI/tree/master/examples/Vitis-AI-Optimizer/vai_p_pytorch/cifar10_ddp) example, the program stuck in the last step of analyse so I must k…
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Currently we have a small exchange memory mapped both in the Microblaze and host address spaces to hold configuration data. The size of this memory is limiting, e.g. some users might need much more me…
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Hi,
I ever installed the old version of the NPU driver, and recently, according to this [page](https://github.com/Xilinx/mlir-aie/blob/main/docs/buildHostLin.md), I updated the Linux kernel(6.10) a…
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I am trying to open the Vivado project to see how it is configured and modify it, but I can't get it openned. I am following the steps mentioned [here](https://xilinx.github.io/kria-apps-docs/kd240/bu…
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Context Parameters using **Implicit Definitions** `implicit` Scala 2, have been reworked in Scala 3 as **Given Instances** `given`. There is a decent amount of rewrite needed for migrating to **Given …