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Hello,
I've been exploring the SYNTCOMP rules page. According to the [Rules in LTL Categories](http://www.syntcomp.org/rules/) section, it is stated that, "_Like in the AIGER category, realizabilit…
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Hi @mvcisback and thank you very much for releasing this useful package!
The install instructions for this package and for your py-mdd package currently require dd < 0.6. Could these be updated to…
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Hi, I have noticed that you were planning to add the features of AIGER support. However, I didn't find any usage in doc, any suggestions? Did it has been implemented?
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**Describe the bug**
What went wrong? (e.g. the optimized circuit was not equivalent to the original one, an assertion failed, etc.)
**To Reproduce**
Steps to reproduce the behavior:
```c++
#in…
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Hi,
For this .aig model:
```
aig 1 0 1 1 0 0 1
0
0
3
```
(corresponding .aag model is:
```
aag 1 0 1 1 0 0 1
2 0
0
3
```
)
abc thinks the model is safe:
```
$ ./abc/abc -c "read redu…
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https://github.com/YosysHQ/yosys
https://www.zhihu.com/question/26742670?sort=created
https://zhuanlan.zhihu.com/p/399378479
- yosys只负责verilog到网表的部分，布线要用[nextpnr](https://github.com/YosysHQ/nextpnr…
cisen updated
2 years ago
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Hi, any possibility to support visualizations of AIGER files, like [`aigtodot`](http://fmv.jku.at/aiger/)?
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Hi, I have an int2float circuit, I transformed it in to aiger by yosys, then I want to synthesize it through abc.
When I try "rf" or "resub", it will trigger **Abc_AigUpdateLevelR_int: Assertion `A…
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Hello,
I would like to use DeepGate2 to generate circuit embeddings for my task. Could you please tell me the versions of the packages that the code depends on, especially the ones related to PyTor…
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Currently the parser uses the toposort_flatten from the toposort library
https://github.com/mvcisback/py-aiger/blob/19b3fe3837c3187dec08a5b58ba7cb36ca107c8d/aiger/parser.py#L367
However, I noticed…