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I'm trying to modify a layout of one of the standard cells in the freepdk45. I'm having trouble adding a new library into Cadence Virtuoso using the technology file found in `OpenRAM/technology/freepd…
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Currently Klayout LVS script extracts pmos_5p0 and nmos_5p0 models for 5V transistors (see [here](https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/74e4ec59b55bcf5be2f153abff8519d…
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@rmanohar I will implement it but i wanted to get your ok/opinion first. also any wishes for the char that i use as flag?
**Describe the bug**
cadence xelium/spectre and for some parts innovus do…
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I found 'skillbridge' with a google search 'skill python cadence' and I am thinking it could solve my issue.
I've created a tkinter dashboard GUI for keeping track of layout verification results. …
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one example is:
i select an voltage source and deselect it after. after deselecting the circle is missing.
![normal](https://github.com/StefanSchippers/xschem/assets/120017377/6d20f083-1eee-44c5-8e…
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Did some more digging after my comment on issue #49
It looks like a few issues.
Basically my goal is to `stream-in` my GDSTK-authored GDS/OAS files into Cadence Virtuoso (presumably openAccess for…
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Hi, I am wondering if ALIGN can be loaded to work with custom PDK in the Cadence Virtuoso, e.g., with NCSU_45_FREEPDK. Thanks!
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### Bug report
**What is the problem?**
It was noticed that the AC mesh is no longer booting when it is upgraded to gluon 2022.1.2. This was also noticed on following other devices (but debuggin…
ecsv updated
11 months ago
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**Problem Statement**
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Each SKILL++ package should be able to add customizations to the Cadence Virtuoso Library Manager.
**Proposed Solution**
----------------…
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Hi @smuellerDD, Please forgive maybe the mistake of opening an issue here.
I am stuck on GRUB boot after I enable LRNG on OpenWrt x86_64 Linux 6.1.47.
LRNG Version: v50
Patch Files: https://git…