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We have a temporal cache with the following settings:
```
items = 7000
block_size = 21846
expires = 900
bitmap=1
ignore_full=1
```
Once we introduced this cache to our system it eventually/randomly…
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**Describe the bug**
Running `./create_venv,sh` now fails to install PyTorch.
```
./create_venv.sh
Creating virtual env in: /home/marty/Documents/tt-metal/python_env
Forcefully using a versi…
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쥐피티가 도와줬어요
```bash
#!/bin/sh
# CPU 개수 확인
cpu_count=$(ls /sys/devices/system/cpu/ | grep -c '^cpu[0-9]\+$')
# 캐시 인덱스 개수 확인 (CPU0 기준)
cache_count=$(ls /sys/devices/system/cpu/cpu0/cache/ | g…
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Hi charles,
I have some doubt regarding L1 and L2 cache sets and cache line in each set of L1 and L2 data cache. can you please help me to clarify the doubt.
Is single cache line size of both…
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### 🐛 Describe the bug
[inductor_single_run.sh](https://github.com/chuanqi129/inductor-tools/blob/main/scripts/modelbench/inductor_single_run.sh)
The Bad Commit:
8458980bbf78714a0fbe703785c100cad…
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Hi, I use the [master](https://github.com/leejet/stable-diffusion.cpp/commit/4a6e36edc586779918535e12b4fbe0583044ee6f) branch to do `text2img` task but the generated images seem unusual.
I build repo…
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I'm running the OpenVLA policy on a machine with RTX4090 with 24GB GPU memory, but the inference is only about 4.4 actions/s after warmup. Am I doing something wrong here?
GPU info:
```
+--------…
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I'm trying to boot zephyr SMP on a non-cache coherent multi-core Cortex-R52 platform. Even with disabling the data cache for all cores, still zephyr crashes on the secondary cores. It turns out that t…
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### 💡 Your Question
Hi, I need some help with training a model. I've tried training with a custom script, but got NaN and 0 loss values during training, so I figured that the problem might be either …
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### 🐛 Describe the bug
I used Hugging face training code.
I found during backward of training by using FSDP, the AllGather kernel doesn't overlap CatArrayBatchedCopy kernel. I don't know why.
s…