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SFC doesn't just disallow name shadowing, it doesn't allow any two things to have the same name:
```
circuit foo :
module foo :
input p: UInt
when p:
wire x: UInt
when p:
…
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I've noticed that a few FIRRTL transforms take a good amount of time to run (depending on the design, of course). One of the most expensive ones is consistently `DedupModules`, which [runs before High…
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For any non-trivial design, the sizes of bundles can get very, very large. This is particularly apparent for modules which use libraries which auto-generate a ton of ports and put them all in the same…
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FIRRTL spec only covers this for modules, and use on extmodule's in untested and unverified.
The following parses and compiles fine:
```firrtl
FIRRTL version 4.0.0
circuit EL:
extmodule X…
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The FIRRTL output got dropped in #80
Please comment here if you would like it back.
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As you obviously know FPGA and ASIC world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help ever…
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I'm trying to have FIRRTL automatically generate a scan chain when a "scan" bundle is included in my design.
Scan bundle = list of signals I want to have custom values for.
But since the added…
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It seems that most but not all FIRRTL statements have an informative "info" field. Some don't.
High FIRRTL has many annotations, but some assignments aren't annotated with the source filename, line, …
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See #171
When you run the FIRRTL/barstools compiler, it needs to depend on all SBT projects that do an `addResources` or `setResources` call (needs to add the other SBT projects to the compiler cl…
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Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:
* ~Unscheduled DFCIR~ Closed with #25 and #31.
* ~Scheduled F…