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It seems that most but not all FIRRTL statements have an informative "info" field. Some don't.
High FIRRTL has many annotations, but some assignments aren't annotated with the source filename, line, …
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Since Chisel has supported LTL via intmodule, I think it might be a good idea to upstream LTL as a part of firrtl spec. This cleans up the fir file generation, and makes LTL->SVA flow more clean and e…
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Branches
| project | branch |
| ------- | ------- |
| firrtl | intervals |
| chisel3 | interval-type-2 |
| firrtl-interpreter | instrumenting-sizes |
chick updated
6 years ago
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Hello, I am very sorry to bother you. I have seen your paper "Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems " and I’m very interested in your Chiffre Fault Injection F…
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I have an internal signal:
`val state = Vec(Reg(init = Bool(true)) +: Seq.fill(p.numBits)(Reg(init = Bool(false))))`
In the PeekPokeTester, I try
`peek(c.state)`
and get
```
[info] - should gene…
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As you obviously know FPGA and ASIC world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help ever…
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Currently, the FIRRTL exporter will not properly unique names during emission (like what `ExportVerilog` does). Consider the following:
```mlir
firrtl.circuit "Foo" {
firrtl.module @Foo() {
…
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See #171
When you run the FIRRTL/barstools compiler, it needs to depend on all SBT projects that do an `addResources` or `setResources` call (needs to add the other SBT projects to the compiler cl…
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FIRRTL memories that do not go through the `--repl-seq-mem` path to replace them with blackboxes always produce a wrapper module around the memory. However, this can result in poorer performance for V…
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The FIRRTL output got dropped in #80
Please comment here if you would like it back.