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Are there any examples of programming an OrangeCrab using the soft RISC-V core, but with custom "gateware" for hardware accelerated peripherals? My goal is to largely program using C/assembly, but to …
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When I use a freshly programmed FPGA (fresh HyperRAM controller), and then read the control registers, the value of the first read at the first control register is wrong:
```
Control Registers: …
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my environment is a Pi4, 8G with a fresh install of Bullsye 64bit.
I've been through the ./install.sh script but so far I've not been able to run cariboulite_test_app due to a `module insertion 'smi_…
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Theoretically it should be (given the lazy programming feature is available in runtime), but need to double check / at least layout how things should be called.
The precise questions are:
1. Are t…
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Hello and thank you for writing!
In general, supporting a different development board is not too complex, but there are three requirements:
1. The FPGA (programming logic) must have direct access …
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Good day!
Sorry for the stupid questions! This is my first FPGA and I'm just starting this journey.
I followed your tutorial, but flashed the STM using ST-LINK.
I was able to build a binary file af…
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Estimados Amigos:
Hace 2 días finalmente llegó mi placa Cariboulite, y estoy muy contento de haberla recibido, pero no logro hacerla funcionar.
La tengo instalada en una Raspberry PI Zero, y he …
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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Hello,
I have a few questions regarding the SDC constraints for the implementation stage.
I am hardening the individual blocks (sb, cb, grid_clbs, and IO pads) separately. Then I will include all …
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I am trying to implement a script in Python which detects Wi-Fi signal.
How to implement it? If I set
```
device_args = {"driver": "Cariboulite"}
sdr = SoapySDR.Device(device_args)
# Set samp…