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Version found: 3.3.4
CMSIS-SVD peripherical definition:
` `
` DDR_III_LPDDR_II`
` DDR3/LPDDR2 address space.`
` 0x40000000`
` `
` 0`
` 0x80000000`
` buffer`
` `
` …
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Tried to execute code (the one in the Xilinx repository) with newest version of RFNOC after having applied your patch to uhd-fpga. However the design does not synthesize.
I believe that the changes…
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I write Verilog modules on Vivado and some of them are a little complex, so testing them on python will be great
When I saw your repository I was so glade and I hoped I could use it, but I found it…
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Allowing to leave out signals that are not strictly required can increase the flexibility of the standard. As a point of reference, I believe only the tvalid signal is actually required in the AXI4 St…
olofk updated
2 years ago
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According to TS 129 244:
- 6.2.6.3 PFCP Association Setup Initiated by the UP Function
- ~~6.2.7.3 PFCP Association Update Procedure Initiated by UP Function (see Graceful Release)~~
- 6.2.8 PFCP As…
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### Description
`typst 0.11.1 (50115102)`
I am not sure if the source of the bug is in the typst compiler or in the https://github.com/andreasKroepelin/polylux package.
```typ
#import "@previe…
m-kru updated
1 month ago
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- [x] #1717
- [x] #1729
- [x] #2321
- [x] #2354
- [x] #2366
- [x] #2394
- [x] #2427
- [x] #3068
Notes:
Disable gssmode for connection
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A common request is to provide hierarchy information for a design.
E.g., for a given design, you'd like to have a representation of the design that includes who instantiated what. This format coul…
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I am facing a problem which is much larger than I anticipated it being: module parameterization or -- more generally -- configuration of the subsystems we produce. The SystemVerilog we have is intende…
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Current Version commit b3bdff1
I am trying to use the stitched IP approach for a non-PYNQ FPGA board. I can successfully output the stitched IP design but when IP-XACT is generated it doesn't have …