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Verilog like parameters for module for debugging purposes.
**Type of issue**: feature request
**What is the use case for changing the behaviour?**
It would be great to have a possibility to ser…
Nic30 updated
5 years ago
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This is a proposal for a new testers API, and supersedes issues #551 and #547. Nothing is currently set in stone, and feedback from the general Chisel community is desired. So please give it a read an…
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## Issue
Rigetti hardware provides XYGate and CZ natively. QuantumCircuit that contains CX gate should be transpiled into those for a more accurate representation of what's being run on the hardware.…
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## Issue Description
In my tests, MPSCircuits take much longer to get jitted than the same circuits. For example, within 2 minutes for a default-type circuit of 8 qubits, but at least more than 40 …
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Hi,
I have tried to get componant value as we can do in ngspice but it does not return anything
Example
a verat basic simple netlist
V0 1 0 5
R1 1 0 100
.tran 0.001 50 uic
Your plug-in giv…
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### Environment
- **Qiskit Terra version**: 0.36.1
- **Python version**: 3.7.4
- **Operating system**: Windows
### What is happening?
When initialize the qubits in a circuit as follows,it…
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Hello, I hope you are having a great day. I am trying to compare the waveforms of the test circuit (I found out it was a counter) with the waveform of the ouput of the eFPGA after simulation, after fo…
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Due to the mechanics of the simulator, RS nor latches do not have an "unstable" state, and so memory chips cannot be created.
![image](https://user-images.githubusercontent.com/47645356/218620830-ef2…
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### Informations
- **Qiskit Aer version**: 0.3.2
- **Python version**: 3.7.4
- **Operating system**: ubuntu 18.04.3
### What is the current behavior?
I encounter a problem using Aer…
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I've tried Digital looking for a more modern version of Logisim and that's how I ended up here. This is my feedback after trying my usual workflow for a short time. I hope you don't find this post too…