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Can we use upstream prjxray in .gitmodules, i.e. `url = git@github.com:f4pga/prjxray.git`? Note, kintext-chatter:nextpnr-xilinx has its own submodule of a customized repo::branch *prjxray-db::k325*. T…
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nextpnr-ecp5 with the --gui parameter launches the GUI app, but it's extremely unresponsive.
OS: Arch Linux
Built from: https://aur.archlinux.org/packages/nextpnr-git/
The application takes over …
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When I launch nextpnr, the following error shows up:
```
❯ /usr/local/bin/nextpnr-ice40
dyld: Library not loaded: @rpath/libQt5OpenGL.5.dylib
Referenced from: /usr/local/bin/nextpnr-ice40
Rea…
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When building with nextpnr-ice40 in version .9 and .10 I get warnings such as:
"Warning: unmatched constraint 'clk_in' (on line 5)" for each set_io line in the .pcf.
You can still build and upload f…
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Not sure if there's something unique about my setup, but for posterity's sake, I wanted to show how I was able to build nextpnr after upgrading to Ubuntu 20.04.
With Ubuntu 20.04 installed, nextp…
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Tang Nano 20K is a development board, using the [GW2AR-18 QN88] FPGA, containing 20736 LUT4 logic cells and 15552 Filp-Flops.
Dertails can see;https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/n…
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`yosys` creates a file with LDCE primitives, apparently `nextpnr-xilinx` doesn't support them.
The command:
```
nextpnr-xilinx --chipdb /home/ildus/dev/nextpnr-xilinx/xilinx/xc7a35t.bin --xdc art…
ildus updated
2 years ago
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## Current Status
In 7-series and UltraScale+, some cells have placement rules that the current FPGA interchange does not express. Following these rules are important for good clock placement. In…
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I run the command
```
/home/mike/git/daveshah1/nextpnr-xilinx/nextpnr-xilinx --chipdb /home/mike/git/daveshah1/nextpnr-xilinx/xilinx/xc7a100t.bin --xdc src/queens_top.xdc --json queens.json --write …
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When compiling on a Mac using Conda, the resulting `pytrellis.so` cannot be used.
The library has correct bindings to `libboost_python3.7.dylib` and to `libpython3.7m.dylib`, however it gives the e…