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gatecat
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nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
ISC License
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Is vivado indirectly required?
#82
Kreijstal
opened
3 weeks ago
2
Site_type Ingestion Confusion
#81
fred-freeman
closed
3 months ago
1
pack.cc: fix wrong attribute name for negedge FFs
#80
hansfbaier
opened
5 months ago
0
implement MMCME2_ADV for xc7
#79
hansfbaier
opened
6 months ago
0
Fix warnings and dsp
#78
hansfbaier
opened
7 months ago
0
Error when adding PLLE2_ADV in xc7a35
#77
jtplaarj
opened
7 months ago
3
Implement CFG_CENTER primitives
#76
hansfbaier
opened
9 months ago
1
Tristate control signals are inverted in designs routed with router1
#75
hansfbaier
closed
10 months ago
3
Assert/Debug fixes
#74
hansfbaier
closed
10 months ago
1
Placer does not terminate for example design
#73
hansfbaier
opened
11 months ago
3
fasm.cc: add TDMS_33 support and fix LVDS_25
#72
hansfbaier
closed
1 year ago
2
fix: ODDR was not useable on tristate outputs
#71
hansfbaier
closed
1 year ago
0
One chipdb, multiple package
#70
trabucayre
opened
1 year ago
0
working patch for latest RapidWright (2022.2.2)
#69
burntfalafel
opened
1 year ago
0
Failure in generating xczu7ev.bba
#68
burntfalafel
opened
1 year ago
0
How do I get this chipdb file: xc7a35t.bin?
#67
JamesTimothyMeech
closed
1 year ago
2
Support negedge FFs
#66
hansfbaier
closed
1 year ago
0
FDRE_1 can't be written out to fasm file
#65
jrsa
opened
1 year ago
8
DSP48E1 works on Xilinx 7 series
#64
hansfbaier
closed
1 year ago
6
Add Spartan7 support
#63
hansfbaier
closed
1 year ago
0
ODELAY implementation works
#62
hansfbaier
closed
1 year ago
1
XC7 IDDR works!
#61
hansfbaier
closed
1 year ago
0
Implementation of the DRIVE attribute of IO pads
#60
hansfbaier
closed
1 year ago
1
XC7 ODDR implementation
#59
hansfbaier
closed
1 year ago
1
router2 does not stop when it visited the source wire when routing backwards
#58
hansfbaier
opened
1 year ago
0
Big incompatibility of the code structure with the actual NextPNR
#57
zipotron
closed
1 year ago
2
Sync upstream
#56
mmicko
closed
1 year ago
68
DDR3 is now working on the high performance banks
#55
hansfbaier
closed
1 year ago
1
ERROR: Invalid global constant node 'INT_L_X0Y112/VCC_WIRE'
#54
Demindiro
opened
1 year ago
0
xilinx/fasm.cc: fix regression (broken DDR3 on high range banks), and other bugs
#53
hansfbaier
closed
1 year ago
0
xilinx/python/xilinx_device: fix fabricname extraction
#52
trabucayre
closed
1 year ago
0
Don't generate OUT_DIFF inside part of the IO tile, which does not exist
#51
hansfbaier
closed
1 year ago
0
fasm.cc: Generate drive bits for SSTL io standards
#50
hansfbaier
closed
1 year ago
0
fix not working SSTL15 input when the pin is on Y1
#49
hansfbaier
closed
1 year ago
0
Support for the Kintex High Performance Banks (RIOB18)
#48
hansfbaier
closed
1 year ago
0
chip-db (bba or bin) files missing
#47
zipotron
closed
1 year ago
3
Cannot use OSERDESE2 in MASTER-SLAVE configuration to support 10-to-1 bit serialization
#46
jhladik
opened
1 year ago
1
Merge in some of upstream nextpnr's CMakeList.txt
#45
LAK132
closed
1 year ago
0
terminate called after throwing an instance of 'std::out_of_range'
#44
Pocketkid2
opened
2 years ago
0
Packer aborts on failed assertion because of uninitialized Arch.site_by_name
#43
hansfbaier
closed
2 years ago
0
Constraints issue using generated chipdb file
#42
Pocketkid2
opened
2 years ago
1
fix: patch export for xc7a35t fabric
#41
Xiretza
closed
2 years ago
0
Handle CRLF line endings in xdc files
#40
LAK132
closed
2 years ago
0
fix: no .IN bit set for LVCMOS12/15/18
#39
hansfbaier
closed
2 years ago
0
Update bbaexport.java
#38
the-centry
opened
2 years ago
0
bbaexport.jar compile failed!
#37
the-centry
opened
2 years ago
1
nextpnr-xilinx crash when using 1.8V input pin on a Kintex 7 325T fpga
#36
infphyny
opened
2 years ago
0
`bbaexport.py` fails for `xc7a35t`
#35
ajelinski
opened
2 years ago
2
Placer fails with long CARRY4 chains
#34
kazkojima
opened
2 years ago
4
Adapt to updated prjxray filestructure
#33
unbtorsten
closed
2 years ago
0
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