-
I want to compile the source code in riscv-ovpsim/source for a new excutable file, but I do not know the build steps. I think a main source file should be composed first.
Could you tell me some tips …
-
Hi,
I 'm trying to run the coremark on the risc-v processor shakti c-class processor on FPGA.
I used your code under this project.
And below are the flags i used.
-DFLAGS_STR=""-O2 -mcmodel=medany…
-
Does riscv-gcc support -fschedule-insns or -fschedule-insns2? The reason I ask is my applications are often accessing stuff that aren't in the cache yet (i.e. random accesses). For this reason, I trie…
-
Hello, thanks for the work I used it for an processor and assembler introduction course it's great. :)
PR: #79
I got an error while trying to execute `example/timertool.s`
```txt
Error in /ho…
-
Hi Vuong,
It's me again from issues #6 and #5. I got back to this project recently and was revising everything.
I wanted to ask about measuring the performance of ztachip. My main goal is just t…
-
In BlackParrot testing with Dromajo cosimulation, at least one test reports out an invalid CSR read for the CSR with address 0x3b0 due to it being unimplemented in the processor.
Reproduce:
checko…
-
when i run make ICESTICK and it show fail
./PROCESSOR/femtorv32_quark.v:68: warning: Attributes are not supported on net declaration assignments and will be discarded.
ARCH=rv32i
OPTIMIZE=-Os
ABI=…
-
### Resource Title
learn-FPGA episode II: pipelining
### Resource Description
This tutorial explains how to transform the basic softcore from [episode I](https://github.com/BrunoLevy/learn-fp…
-
### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have up…
-
Are there any examples of this? These kinds of spreads seem overly complex to me. I'm sorry for asking such a stupid question. Do I need to install a program like Verilator while using this? I designe…