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So, this is a pretty big challenge I think....
The iCE40 1K has the following resources;
* 1280 Logic Cells
* 64kbits Embedded RAM bits
* 1 PLL
However, there might be hope, your stats …
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Recently when I compile the RISC-V toolchain, I cannot get caravel_board examples to compile unless I modify the compile line to change `-march=rv32i` to `-march=rv32i_zicsr`.
Apparently this is be…
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`I-RF_x0-01` has trouble building with what looks like a sign extension issue:
```
ERROR: /usr/local/google/home/drewmacrae/opentitan/third_party/riscv-compliance/BUILD:9:21: Compiling riscv-test-su…
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I am using RISCV-ISAC to generate the add instruction coverage. I found that some checkpoints in CGF are 0, but it is obvious from the assembly file that this constraint is satisfied. Is this normal?…
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when i run make ICESTICK and it show fail
./PROCESSOR/femtorv32_quark.v:68: warning: Attributes are not supported on net declaration assignments and will be discarded.
ARCH=rv32i
OPTIMIZE=-Os
ABI=…
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Hi,
CHERIoT is spec'ed as being 16 GP registers only. However, in Sonata the RV32E is set to 0 which means that there are 32 GP registers. Shouldn't the RV32E parameter be set when the CHERIoTEn pa…
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On RV32IC architectures, the SAIL model currently fails with the following messages:
```
/path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: Assembler messages:
/pa…
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The variable 'xlenlim' referenced in the abstract combination of a few bitmanip instructions within the configuration files rv32i_b.cgf, rv32e_b.cgf, and rv64i_b.cgf appears to be "not defined", leadi…
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I found that you are working on ztachip.I got issues with the micropython
I have done the ztachip build process , standalone image is working fine.
While going with micro-python ,I followed these st…
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Hi,
I'm trying to build the pk/bbl to a 32-bit target but I think that the right argument it's --with-arch=rv32ima instead of --enable-32bit, also the libs like gcc are not pointing to the right path…