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Example here
https://ganeshgore.github.io/spydrnet-physical/auto_openfpga_basic/04_fpga_grid_render.html
Following line in the code should create a new SVG symbol and replace existing cbx_1__0_ an…
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Unable to generate a TMR netlist
ValueError: Applying name would result in a naming conflict
namespace_manager -> __init__.py
Line 107 - if parent and parent in self.namespaces:
possible …
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Now that SpyDrNet doesn't support Python 3.5, some SpyDrNet-TMR tests fail for Python 3.5. We should probably just drop support for Python 3.5.
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Right now, the SpyDrNet python package only has EDIF example netlists. It should probably include Verilog and EBLIF example netlists as well. Not only would it be nice to have, but tests in spydrnet-T…
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I tried running an eblif netlist through our TMR tools and it failed. There were several reasons for this:
1. **Finding voter insertion points**
find_after_ff_voter_points() calls load_pr…
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The Verilog parser breaks if the source contains comment after the final `end module
**Steps to reproduce**
1. Create Verilog design.v
```
module MOD2 (A, B);
input A;
input B;
wi…
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I ran into something that seems like a bug, so I wanted to let you know and ask what you think. When I parse one of my ECEN 220 projects into spydrnet, one of the wire connections isn't right.
The …
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It would be awesome to have some tutorials that show up in the documentation nicely. This would hopefully give someone an introduction to SpyDrNet who has never used the tool before.
We already hav…