byuccl spydrnet issues - Githubissues

byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

https://byuccl.github.io/spydrnet

BSD 3-Clause "New" or "Revised" License

86 stars 20 forks source link

issues

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Newest Most commented Recently updated Oldest Least commented Least recently updated

Added default_nettype as a verilog token

#223 ganeshgore closed 4 months ago
0
is_downto flag fix for big-endian bundle declaration

#222 ganeshgore closed 3 months ago
0
Incorrect handling of big-endian declaration (is_downto=false)

#221 ganeshgore closed 3 months ago
5
Flatten cannot handle multiple instances of one definition in another definition.

#220 zhuguiyuan opened 4 months ago
2
Fix version string on non-master branch to comply with PEP440

#219 jgoeders closed 8 months ago
0
`setuptools.extern.packaging.version.InvalidVersion` on `next_release` branch

#218 jgoeders closed 8 months ago
0
Add python 3.11 to CI

#217 jgoeders closed 7 months ago
0
`\<const0>` and `\<const1>` missing drivers

#216 jgoeders closed 8 months ago
3
EDIF files generated by Atmel CPLD fitter unparsable.

#215 peterzieba opened 8 months ago
11
Verilog: Support concatenation in assign statements

#214 jacobdbrown4 closed 8 months ago
1
Getting recursion error when parsing a netlist

#213 arun-chaubey opened 8 months ago
7
`requests` package dependency not in setup.py

#212 jgoeders closed 8 months ago
2
Handle(again) params in module's body and multi-entry assigns in Verilog parser

#211 Chopper455 closed 8 months ago
5
Handle params in module's body and multi-entry assigns in Verilog parser

#210 Chopper455 closed 9 months ago
0
Handle params in module's body and multi-entry assigns in Verilog parser

#209 Chopper455 closed 9 months ago
0
SpyDrNet 1.13.0

#208 jacobdbrown4 closed 9 months ago
0
Create CoLab examples

#207 wirthlin opened 1 year ago
0
Move Tests Out of the Package

#206 jacobdbrown4 closed 1 year ago
5
SpyDrNet 1.12.2

#205 emonlux closed 1 year ago
0
SpyDrNet 1.12.2

#204 emonlux closed 1 year ago
0
Include type hinting

#203 agg23 opened 1 year ago
1
Handling Intel architecture definitions

#202 agg23 opened 1 year ago
1
[verilog] Primitives

#201 agg23 opened 1 year ago
4
Zipped support files

#200 agg23 closed 1 year ago
6
[verilog] Fixed parser not properly handling empty instance port list

#199 agg23 closed 1 year ago
0
Wrong pin indexing on partially connected output port

#198 jgoeders closed 1 year ago
5
Instance names have space at the end

#197 jgoeders closed 1 year ago
4
Distinguishing pins in multi-bit ports

#196 jgoeders opened 1 year ago
5
parse should work with Pathlib.Path

#195 jgoeders closed 1 year ago
10
SpyDrNet 1.12.1

#194 jacobdbrown4 closed 1 year ago
0
SpyDrNet 1.12.0

#193 jacobdbrown4 closed 1 year ago
0
Delete Old Branches

#192 jacobdbrown4 opened 1 year ago
5
Transformation to and from EBLIF

#191 emonlux opened 1 year ago
1
Added sort all flag to the Verilog composer

#190 ganeshgore closed 4 months ago
3
Composer skip constraints

#189 ganeshgore closed 9 months ago
1
[Bugfix] constant net name

#188 ganeshgore closed 1 year ago
1
Strict code formatting

#187 ganeshgore closed 9 months ago
5
Added pytest for multiple wire declaration

#186 ganeshgore closed 9 months ago
1
Make SpyDrNet internals completely generic

#185 jacobdbrown4 opened 1 year ago
2
Verilog Composer Writing Module Header Port Concatenations

#184 jacobdbrown4 closed 1 year ago
2
Issues parsing F4PGA-generated reverse-netlists.

#183 Dumbledork01 closed 1 year ago
2
Case Sensitivity - EDIF composer

#182 emonlux opened 1 year ago
10
Verilog parser not parsing file

#181 emonlux closed 1 year ago
2
Hierarchy Support in BLIF/EBLIF

#180 jacobdbrown4 closed 1 year ago
1
Built-In Primitive Library FPGA Architecture libraries

#179 jacobdbrown4 closed 1 year ago
3
Setting correct top module when parsing netlist from Lattice

#178 jacobdbrown4 opened 2 years ago
4
Verilog parsing fails when ports implicitly mapped

#177 jacobdbrown4 closed 2 years ago
1
Initial support for case insensitive naming

#176 slide closed 1 year ago
5
SpyDrNet 1.11.1

#175 jacobdbrown4 closed 2 years ago
0
EBLIF parser and composer not included in 1.11.0 python packages

#174 jacobdbrown4 closed 2 years ago
1