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What is the current thinking on putting hard cores on the Metlino/Sayma/etc.?
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use dma ip ,the driver,examples worked well, but vdma cant:
Z-turn# ./axidma_benchmark -v
AXI DMA Benchmark Parameters:
Transmit Buffer Size: 7.91 Mb
Receive Buffer Size: 7.91 Mb…
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I've just pushed the commit.
IO Firmware will display OSD with list of cores if core MENU is loaded.
I think, some users (including me) would like to have OSD displayed at startup with core choice.
H…
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With a standard Vivado installation, in order to rebuild the FPGA bitstream with the make_bitfile.sh script,
you need to add the correct 'board definition file' for the microzed (or other platform lik…
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The Xilinx Zynq-7000 series devices are a combined ARM processor with a "series 7" FPGA. The [Digilent ZYBO](http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO) is a very chea…
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Update(7-marts-2016)
first working beta3 image online.
MK PR passed build tests.
ready for signoff.
https://drive.google.com/file/d/0BwyLvgyVIdi8WFBraENyZ0dQUXc/view?usp=sharing
https://drive.goog…