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I have a question about the non-pipelined version: Why do you use 7 FPGA cycles? Because when I run the design on my FPGA (Ultra96-V2), I get an interval of 5. I can use #pragma HLS PIPELINE II=4 inst…
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** Which tutorial are you running? **
https://github.com/Xilinx/Vitis-Tutorials/tree/2022.2/Hardware_Acceleration/Design_Tutorials/10-get_moving_with_alveo
** Describe the issue **
It fails on sw…
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**Describe the issue**
I was able to successfully run the "**13-aie-performance-analysis**" on both Hardware emulation and actual hardware with out any modifications. But If I use the `event::start_p…
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ex. csv, json or something idk?
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I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, bu…
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I installed ubuntu 18.04 virtual machine on vmware, and installed vitis 2023.1 on ubuntu.
When I building from source following https://pavel-demin.github.io/red-pitaya-notes/sdr-receiver/
I could …
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Hi,
I am performing training procedure for the caffe model i.e. 01-caffe_cats_vs_dogs. I am facing below issue during training.
I0210 09:24:31.278432 2794 caffe.cpp:247] Starting Optimization
I0…
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Hi,
This is my first time working with Vitis, so maybe this is a dumb question... But the wrapper project is failing to build from a fresh clone of this repo, and I'm wondering what I'm missing? …