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Since doing the slave FPGA loading rework and upgrading to the latest master, I've started seeing PRBS errors roughly 100% of the time on boot. I never saw that before. Not sure if it's due to the rew…
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- [ ] BaseMod and MixMod should have a single >=1MSPS 16-bit ADC with 1 channel per input (simultaneous sampling)
- [ ] Use a an ADC with a nice LVDS interface, such as LTC2324-16
- [ ] Optimize lay…
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Moving from m-labs/artiq for now as this may be a hw issue.
@gkasprow:
- I remove the jumper on the programming connector to re-enable the RTM Exar chip, but left the 2V and 4V rails disconnected.…
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Using Windows 10 artiq 3.2
```
>artiq_session
Traceback (most recent call last):
File "C:\Users\monroe\Miniconda3\envs\artiq-dev\Scripts\artiq_session-script.py", line 11, in
load_entry_po…
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Per issue #62, it's an [oversight](https://github.com/m-labs/migen/issues/62#issuecomment-350777380) that `CALL_FUNCTION_KW` and `CALL_FUNCTION_VAR_KW` are not supported when searching for variable na…
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I was wondering if you ever got this frequency counter functioning to your satisfaction... I was about to implement something similar when I saw this repo! Were you able to get similar speeds to what …
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I am very impressed with your project, great job on the documentation! I thought would let you know that there will be an Open Hardware dev room at FOSDEM next year. Call for participation is availab…
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https://bugs.python.org/issue27213 breaks fhdl.tracer.
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placement of MMCX connector is too dense - one won't be able to plug or unplug them.
![obraz](https://user-images.githubusercontent.com/4325054/30655781-3cff5078-9e32-11e7-9fd0-8a280d90ba01.png)