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m-labs
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migen
A Python toolbox for building complex digital hardware
https://m-labs.hk/migen
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Async FIFO Output is Broken when FIFO Depth is Set to 2
#296
linuswck
opened
1 day ago
0
Fix Signal initialization when max=1
#295
andelf
closed
3 weeks ago
4
Implement almost_full and almost_empty for Synchronous FIFOs
#294
occheung
opened
1 month ago
0
Ebaz4205 update2
#293
newell
closed
1 month ago
3
fhdl/structure: add check for equality for _Slice
#292
maass-hamburg
opened
2 months ago
4
zc706: AJ7 net name fix
#291
MorganTL
closed
2 months ago
2
Refactor PS portion to migen-axi
#290
newell
closed
3 months ago
0
fhdl/tracer: handle `STORE_DEREF` for local, cell, and free variables
#289
fsagbuya
closed
4 months ago
0
Python 3.12 namer issue
#288
sbourdeauducq
closed
4 months ago
0
EBAZ4205 update1
#287
newell
closed
4 months ago
0
Add EBAZ4205 board to platforms.
#286
newell
closed
4 months ago
0
FSM.ongoing is broken or...
#285
shareefj
closed
5 months ago
2
Updated EEM FMC Carrier platform for v1.1
#284
kaolpr
closed
6 months ago
0
migen/fhdl/tracer.py: update get_var_name() from amaranth
#283
maribu
opened
10 months ago
0
pyproject.toml: add build backend
#282
gsomlo
closed
11 months ago
0
feature: add Module.print_hierarchy
#281
shareefj
opened
1 year ago
6
kasli_soc: add user_led2
#280
SimonRenblad
closed
1 year ago
4
zc706: correct the speed grade in the fpga part number
#279
linuswck
closed
1 year ago
0
efc: add support for custom platform name
#278
linuswck
closed
1 year ago
1
Add OOB reset user attributes for ARTIQ
#277
occheung
closed
1 year ago
0
Replace setup.py with pyproject.toml
#276
davidbrochart
closed
1 year ago
0
Subvector of Cat() incorrect assignment
#275
noiuynoise
closed
1 year ago
1
`else` branch elided in generated Verilog
#274
McSherry
opened
1 year ago
3
Fix EFC pinout - HB09_N
#273
marmeladapk
closed
1 year ago
0
EFC platform - swap FMC CLK BIDIR polarity
#272
marmeladapk
closed
1 year ago
0
Added support for EEM FMC Carrier
#271
marmeladapk
closed
1 year ago
0
build/tools: language_by_filename, add SystemVerilog extensions to Verilog
#270
JammyL
closed
1 year ago
0
Better FMC support
#269
kaolpr
opened
1 year ago
1
add red pitaya 7020 variant
#268
TopQuark12
closed
1 year ago
2
[Sim] Error with fsm delayed_enter method
#267
kamejoko80
opened
2 years ago
0
Invalid synthesis output for TSTriple width > 1 (Vivado)
#266
kaolpr
closed
2 years ago
1
Problem with an instance
#265
ramalmar
closed
2 years ago
1
Added support for Digilent Genesys 2 platform.
#264
kaolpr
closed
2 years ago
0
Added post synthesis commands to Xilinx Vivado toolchain.
#263
kaolpr
closed
2 years ago
0
Fix ECP5 BRAM packing
#262
madscientist159
opened
2 years ago
2
fhdl/tracer: update to support python 3.11
#261
gsomlo
closed
2 years ago
3
zc706: la26_p pin fix
#260
Spaqin
closed
2 years ago
0
tests fail when building with Python 3.11
#259
gsomlo
closed
2 years ago
4
move the conditional part of `toolchain.build(run=True/False)` to a separate method
#258
lneuhaus
opened
2 years ago
1
Insert a `define in the top scope
#257
smosanu
closed
2 years ago
1
Incorrect simulation of Cat()
#256
enurseitov
opened
2 years ago
3
Unable to build gateware for Kasli v2.0
#255
rgresia
closed
2 years ago
1
sayma_amc2: fix missing FPGA<->CPU SPI pins
#254
HarryMakes
closed
2 years ago
0
vivado: improve timing during opt_design
#253
occheung
closed
3 years ago
0
Instance parameter value needlessly translated to narrowed width causes errors
#252
smosanu
closed
3 years ago
5
zc706: added pmod1 and xadc connector
#251
Spaqin
closed
3 years ago
0
zc706: add user_sma_mgt
#250
Spaqin
closed
3 years ago
0
kasli_soc: cdr_clk: replaced lvds_18 with lvds_25
#249
Spaqin
closed
3 years ago
0
data change issue inside FSM state
#248
jimmymagemtek
closed
3 years ago
0
Signal Names of FSM
#247
navaneeth-cirel
opened
3 years ago
0
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