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I'm trying to port your design from VCU1525 to U280
I have successfully generated bitstream.
But when I try to run bare-metal application using Vitis xsct, there is no output in serial terminal.
I …
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Hi,
I am trying to using Aurora IP with a U250 card following [Using Aurora IP in Alveo with Vitis Flow](https://github.com/Xilinx/Vitis-Tutorials/tree/2022.1/Hardware_Acceleration/Design_Tutorials/0…
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I have been trying to recreate models that can be deployed effectively on the ZCU104 Ultrascale+ MPSoCs (Zynq Platforms). These are CNN models for CV task such as classification and object detection.
…
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Hello and thanks for your work in this repository. I am using Vivado 2018.3 for the VCU1525 board, is there an easy way to port your board files in the older Vivado version?
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I can't build the HW emulation. This error log is from running the code from this repo on a NERC VNC terminal:
```
make all TARGET=hw_emu DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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I want to run LiteX on xilinx_alveo_u200 board.
Since `xilinx_alveo_u200` is not available in LiteX so I have modified from `xilinx_alveo_u250`.
The target file was kept the same as `xilinx_alveo_u2…
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Alveo U200 support seems to be quite straightforward, pins and interfaces are identical to the U250 board, so it's just a matter of changing the board and part number in the Makefile.
I verified that…
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Hi!
I built the code without modification from the main repo with switches:
vivado -mode tcl -source build.tcl -tclargs -board au200 -num_phys_func 2 -num_cmac_port 2
Then implemented the proje…
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Hi,
I'm trying to build the mobilenet-v1 model. I followed all the steps in the README of the repository. However I get this error:
```
File "/opt/conda/lib/python3.8/site-packages/sigtools/…