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When I try to run the commend "pytest", I came up with this error "OSError: libverilogAST.so: cannot open shared object file: No such file or directory", can anyone tell me how to solve this problem ?…
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@jeffsetter @rdaly525 I'm guessing this is related to #108 but there is an error in one of the Harris sch4 compute units:
```bash
ERROR in compute unit: hcompute_cim_stencil
in0_lgxx_stencil[0] -…
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Proposal: `test(mantle.operator.and_, operator.and_, [Bit, Bits, UInt, SInt])`
Where `test(mantle_primitive_op, python_op, types)` will test `mantle_primitive_op` in the Python simulator, Verilator…
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Currently the verilog for commonlib.MuxN is generated like the following:
```
module commonlib_muxn__N2__width9 (
input [8:0] in_data [1:0],
input [0:0] in_sel,
output [8:0] out
);…
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It would be great to have fault generate the relative ordering between all the edges for multiple clocks.
In terms of API, I think something along the lines of:
```
tester = fault.Tester(circ,c…
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@jeffsetter it seems that the ROM outputs for the 1 pix / 3 cycles and 1 pix / 9 cycles coreir output is still not correct:
```bash
%Error: harris_sch4_1pp3c.v:3137:98: Too many digits for 16 bit …
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Not sure why this test is failing, I think I have updated everything.
```
tests/test_deprecated/test_old_io_syntax/test_old_io_syntax_define.py .F [ 20%]
=================================== F…
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See branch `libcoreir-python-travis` for WIP. Currently blocked by linking `-lpython3.7m` inside the manylinux environment.
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https://github.com/rdaly525/coreir/blob/master/src/ir/moduledef.cpp#L114-L132
Should check if prev or next are nullptr before updating the map. Also clarify the logic on the case that the instance …