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Would it be possible to compile nextpnr, in particular nextpnr-ecp5, with GUI support?
According to https://github.com/YosysHQ/nextpnr GUI support is disabled by default to reduce dependencies. It …
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To use litex and vexRiscv there are various build tools required.
The aim for this repo is to build all the required tools into one or more containers to allow quicker build and automated testing o…
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Accurate Verilog FOSS models compatible with Yosys, Icarus and Verilator are needed for the following ECP5 primitives:
- [ ] Block RAM (DP16KD, PDPW16KD)
- [ ] Clocking related components (DCCA,…
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does Trellis/Yosys support LUT6 instantiation for ECP5?
as in: LUT6 #(
.INIT(64’h0000000000000000) // Specify LUT Contents
)
LUT6_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
…
peepo updated
4 months ago
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### Version
Yosys 0.36+85 (git sha1 f26495e54, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
[yosys_crash.zip](https://github.com/YosysH…
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I have Xilinx Kintex XC7K325 board and ECP5 color light 75b board and openFPGALoader works fine with ft2232 cable. However, I am not able to load the bitstream using CH347. I tried both Xilinx and Lat…
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Instantiating a TRELLIS_SLICE on the ECP5 as in https://gist.github.com/newhouseb/784cc0c24f8681c3224c15758be5d1b8 results in
`ERROR: cell type 'TRELLIS_SLICE' is unsupported`
It did work several mo…
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See zero-extend here https://github.com/uwsampl/lakeroad/blob/d6a601ca24356ebb533b10107159845c95f49970/racket/generated/lattice-ecp5-alu54a.rkt#L1770
It's passing a second argument to bv->signal, w…
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We should try and keep the top level directory of the repository relatively clean.
I suggest we do the following;
- [ ] Move `make` to `common/cmake`
- [ ] Move `yosys` to `common/yosys`
- [ …
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Due to the large number of the pins in the new ECP5 boards, the pin's names has to be larger.
Actually Icestudio only shows 5 characters in the pin's field.
Please could you allow to show names with…