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This is just for future reference for topological quantum circuits. A lab mate of mine (https://github.com/rxnew/) has developed a nice code for visualisation of topological quantum circuits which can…
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Example:
The [How to build and transpile Qiskit quantum circuits](https://github.com/qiskit-community/ffsim/blob/main/docs/how-to-guides/qiskit-circuits.ipynb) notebook begins with the markdown
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There is no phase tracking, and no phase gate in the standard set.
It is not a natural fit because it is a non-dataflow global operation. Almost like metadata?
Phase only matters in certain kinds…
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# General Grant Proposal
* **Project:** https://github.com/privacy-scaling-explorations/acceleration-program/issues/12
## Project Overview :page_facing_up:
### Overview
This task intensive…
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Same deal for #1, but with some different things
## GTm texture overhaul
GTM textures are getting overhauled, so the custom circuits and etc will need to be updated to match
- [x] Circuits
- [x] Comp…
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### Environment
- **Qiskit version**: 1.0.2
- **Python version**: 3.11.0
- **Operating system**: Windows 11
### What is happening?
- I have a 4 qubit quantum circuit and a `Statevector` o…
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Warning: spoilers!
Alien Power Augmenter: Default Recipe: no inputs, 500MW output plus 10% of all positive power contributions on the circuit. stacking is additive (so two of them is 1GW and 20%)
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**Is your feature request related to a use case or problem? Please describe.**
As the size of the circuits we build with Cirq increases, the ASCII style circuit diagrams do not scale very well. We al…
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#479 According to the response `_(@damiansteiger),_` the memory issue is related to the number of qubits, with 40 qubits requiring 16TB of RAM. However, I have tested another circuit with 60 qubits an…
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In “tk_to_qiskit”, a conditional gate in TKET circuit transpires a conditional gate of qiskit circuit using bit condition “c_if” on L660-L697 of “qiskit_convert.py”.
https://github.com/CQCL/pytket-qi…