-
Fist of all, appreciate your tutorial ! it is very helpful.
In "Prepare the Network Deployment File", I got following error when building hello_dpu. It seems to be a tiny problem but I have no clue a…
-
官网已经不提供下载了,想要复现您的实验,请问您的安装包还在吗?
-
I am having a Ubuntu 18.04.1 LTS and downloaded SDSoC 2018.3 , I followed the instructions in this link
https://github.com/Xilinx/CHaiDNN/blob/master/docs/BUILD_USING_SDX_GUI.md . But I am getting t…
-
I have a project similar to Xilinx/SDSoC_Examples/cpp/getting_started/data_access_random/src/ which means I want to access arrays randomly.Here is my some code below:
`#pragma SDS data copy(stonesimg…
-
Hi,
While trying to compile and build SD_SOC version of "Digit_recognition" application using G++, compile fails at linking stage with below errors-
```
"digit_recognition.cpp:(.text+0x3d): undef…
-
When I try to run tiny-yolo on Xilinx ZCU102 FPGA, it failed with the error message,
.....
ERROR: No virtual to physical mapping found; Make sure all arrays passed to the
zero copy datamover are al…
-
Hi,
I'm trying to use xf::cv::AXIvideo2xfMat and there seem to be a bug inside the code causing the synthesizer to error.
the error is as followed:
```
ERROR: [HLS 200-977] Argument 'stream_in_1_…
-
Hi there...
I've been trying to get the hello world example to work in vitis 2019 the past day or so. I've ended up finding that these instructions here had a lot of the necessary background that…
-
Hi,
I was trying to run the PLRAM example in the repo, and ran into some issues when compiling it with v++. When I compile the source directly, as https://github.com/Xilinx/Vitis_Accel_Examples/blo…
-
Hello,
I got issue when I was trying to build CHaiDNN version 2 on ZCU104 platform on SDSoC 2018.2.
`===>The following messages were generated while processing /home/anhnt/workspace/zcu104_CHaiD…