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i use the latest rocket-chip and i2c in sifive-blocks to generate SOC,but i2c's output is directly deasserted in the verilog code generated by rocket-chip，as follows ：
.pdf,
on page#12, it says the following for "SiFive U74 Dual-Core":
> CLIC for timer and …
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This issue is intended to track passrate of `riscv-tests/debug` testsuite on SiFive HiFive1 A01
| Version | Report |
| ---------- | --------- |
| e51f8695ed886f9d84cd7a71408822bfb800ac40 | https:…
en-sc updated
6 months ago
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I'm experimenting with the example-pmp demo https://github.com/sifive/example-pmp/blob/master/example-pmp.c. At line 100, it seems ```mcause``` register is not set for me and program doesn't enter ```…
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I'm running into the following error when using the `fillb` command:
```
$ openocd -c " source [find board/sifive-hifive1-revb.cfg]; init; reset init; halt; flash fillb 0x20040000 0xff 512; exit"…
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While building Clang 18.1.8 on a Power9 64-bit PowerPC (big endian) system:
```
[ 23%] Building riscv_sifive_vector_builtins.inc...
#0 0x0000000122b0c3e0 SignalHandler(int) Signals.cpp.o:0:0
#…
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The current tuple syntax involves several kinds of boilerplate:
- Getter/setters are very verbose [1], which decreases readability.
- Sometimes it is difficult as a human to parse the getter/sette…
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The `ModuleInliner` pass crashes with the following MLIR,
`circt-opt --pass-pipeline='firrtl.circuit(firrtl-inliner)' `
```mlir
firrtl.circuit "Inliner" {
firrtl.hierpath @nla_3 [@Bar0::@w, @…
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> https://alive2.llvm.org/ce/z/on8IIK suggests `1