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When I loading the xclbin i found error message below
ethminer 0:01 A0 0.00 cl0 6.00
ethminer Job:46dd6fd4.. f2pool.wanshuawu.xyz[43.129.210.144:6688
ethniner Job:2f21cc97..f2pool.wanshuawu.xyz[…
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我在官网上下载U50对应的ubuntu22.04的对应bed包,安装好后mpd服务无法正常启动,查看发现是/dev/下没有xfpga设备,该设备是如何生成的? 我使用lspci | grep Xilinx 能够获取都fpga信息。
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Loading libraries...
loading function wait_matrix
loading function result_ready
Listening @ localhost:49000 ...
************************************************************************************…
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It seems that `unix_socket::sk_read` in runtime_src/core/pcie/emulation/common_em/unix_socket.cxx does not take into account the possibility of having less data on the socket than required.
The `(r…
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Hello, we have problems setting up the Alveo U250 card to work with the Vitis-AI.
We are using Centos 8 and because we would like to use the latest Vitis and Vivado software alongside Vitis-AI, we …
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I run in ubuntu22.04: Follow the instruction in https://xilinx.github.io/XRT/2022.2/html/build.html
When : sudo apt install ./xrt_202220.2.14.0_22.04-amd64-xrt.deb
There is some problem in xocl a…
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In 'Profiling the Application' of section create my first SDAccel program - The SDAccel.ini has been replaced by the xrt.ini file **SDx 2019** ( [https://www.xilinx.com/support/documentation/sw_manual…
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cover the essential parts of the article.
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Hi team,
I am trying to implement a line-buffer architecture with the data reuse function of the ObjectFIFO, here is a simple example I used to test the architecture.
The input is four vector, e…
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user@user_host:/home/user/GIT/Vitis_Libraries/database/L3/tests/gqe/aggregate$ build_dir.hw.xilinx_u280_xdma_201920_3/test_q1.exe -L 20 -xclbin build_dir.hw.xilinx_u280_xdma_201920_3/gqe_aggr_part.xcl…