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Creating this issue to let the community know about behavior we've seen at DornerWorks and wondering if anyone at the seL4 Foundation has seen this issue as well.
## Setup
There is a Webserver a…
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Hi FINN Team,
I am currently working on a project that is interested in recreating the quantized .onnx file used for the ResNet-50 FINN example here:
`https://github.com/Xilinx/finn-examples/tre…
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Hello and thank you for writing!
In general, supporting a different development board is not too complex, but there are three requirements:
1. The FPGA (programming logic) must have direct access …
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Is ONNX runtime compatible with ZCU102 and other non-alveo/EdgeAI Vitis-AI compatible platforms?
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#### Document Details
* Title: Vitis AI
* Page: [https://onnxruntime.ai/docs/execution-provider…
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hw: zcu102+nvdla
os: ubuntu20.04
Tengine: 1.5-dev
错误信息是double free detected:
![1afe628a390c652751c640996c34b75](https://user-images.githubusercontent.com/30828813/151684968-d9629fa2-de6e-4871-93…
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#### Context
This ticket's part of a debugging effort and connected to past issues including #69 #70 #71 and #72.
While developing kernels it's common to test (also in `hw` target) incremental v…
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I use this model in Xilinx model zoo do quantize and compile for zcu102:
![image](https://user-images.githubusercontent.com/29936604/205812807-8be064db-c780-4602-8e61-d9617222995b.png)
the freeze …
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When I tried running SSD, it is well operating on ZCU102.
On the other hand, other deep neural network including "concat" layer is not working.
- Tiny SSD and etc including general concat.
I …
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Hello,yueniu,
I encountered a error ' design did not meet timing - Design failed to meet timing', and the failed timing checks (paths) is {zcu102_i/conv_fpga_1/inst/grp_conv_ichnl_fu_1422/dataflow_in…
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I am running nvdla_small spec on Xiliinx Ultrascale Board ZCU102
But,There's a problem : NVDLA a0000000.nvdla_small: failed to register drm device。
cat /proc/interrupts is also not right。
Why,how t…
ghost updated
3 years ago