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I'm playing around with the APB stuff in rocket chip and it seems to be leading to some binding problems.
Here is the relevant portion of the stacktrace:
```
chisel3.core.Binding$RebindingExcepti…
grebe updated
7 years ago
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Apparently building the sample RoCC examples using:
% cd vsim
% make make CONFIG=WithRoccExample
do not produce the RTL for RoCC. Is there a patch that needs to be applied? What is the best com…
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This makes it hard to diff your version of common files from rocket, coreplex, config, etc. I am unclear why this extra name specificity when I would assume you could just default this?
Also, why do…
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Hi,
I'm getting an error using the cmd-line below (see (1) below)
cd rocket-chip/vsim
make verilog CONFIG=BOOMConfig
Is there something wrong in my cmd-line setting and what's the correction…
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Hello,
When bulding the FSBL, I got errors for make.
Problems:
```
Description Resource Path Location Type
make: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/make.libs] Error 2 FSB…
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[root@localhost zedboard]# make rocket
bash /usr/local/fpga-zynq/common/generate-pkg-mk.sh testchipip > /usr/local/fpga-zynq/common/Makefrag.pkgs
cd /usr/local/rocket-chip && java -Xmx2G -Xss8M -XX:…
ghost updated
7 years ago
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Hello,
In the emulator/generated-src directory, I didn't find the Chisel generated C++ code, like I'm supposed to in the instructions.
Here's what I find:
```
alpha@alpha-VirtualBox:~/fpga-zy…
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[1]+ Stopped ./emulator-rocketchip-RoccExampleConfig ./pk ./rocket-rocc-examples/build/test-accumulator
real 11m56.553s
user 0m0.000s
sys 0m0.000s
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I couldnt make any new (or even existing CONFIG with modified source code) after I perform make clean.
It will complain missing .fir needed to generate .v file.
Before tried make clean, I couldnt…
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**Output:**
````
[info] [11.192] Done elaborating.
[success] Total time: 121 s, completed Mar 21, 2017 2:02:53 PM
mkdir -p /scratch/celio/firrtl-chip-deleteme/emulator/generated-src/
java -Xm…