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Hi,
I can build BOOMConfig and MediumBOOMConfig in emulator directory but when I used make CONFIG=MegaBOOMConfig in emulator dir, I get the exact same "java.lang.reflect.InvocationTargetException in…
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Hello,
When I run make in the vsim directory, it yields the following:
```
mkdir -p /home/alpha/rocket-chip/vsim/generated-src/
cd /home/alpha/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermS…
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In fpga-zynq we use a serial adapter/tether to write into the L2 of rocketchip.
When i mix the serial adapter traits into my cake i get an exception (below). The same error can also be exercised b…
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I have added the UART scala code from the sifive repo to rocketchip. But the simulation triggers an assertion fail about re-using source ID. Here is the simulation output (I have commented out the sca…
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[bbl](https://github.com/riscv/riscv-pk/blob/master/machine/configstring.c#L9) uses the pattern `ram{0{addr` to search for memory information. However, the configure string output during elaboration l…
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Hello,
I have made the RISCV tools. Added the RISCV and riscvtools/bin to the PATH. Now, when I try to run the asm tests, I get error.
`{txace3:emulator} make
mkdir -p /proj/txace/rocket-chip/emul…
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Hi all,
I have some troubles understanding how the the DRAM is connected with the rest of the system inside U500 VC707 FPGA Dev Kit. Here below there is what I understood (with some guesses).
On…
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Hi,
I'm trying to build the tools in CentOS 6.9. It seems to have a problem with the libusb package, as can be seen below:
```
# ./build.sh
Starting RISC-V Toolchain build process
Removing e…
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I had transplanted the Chisel implementation of sha3 to the current Rocketchip as following:
1, git rocktchip and toolchain, compile them as README.md
2, git rocc-template
3, add Sha3Accel code i…
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I did everything the Readme said, but when I ran the testaccumulator, it never terminated. I gave it 3 hours. Is this something anybody has come across and knows how to fix this? Is there any chance I…