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Using `Verilator` in the `OpenLane` flow produces a linting fail, which is documented here: https://github.com/The-OpenROAD-Project/OpenLane/issues/1811
It seems like `verilated_std.sv` is auto-inc…
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### Description
Hello, I'm trying to install OpenLane I followed exactly the instructions as they are in the github page but when I try to do **### make**, it doesnt seems to work, seems i'm missin…
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It would be nice to be able to generate the same kind of `tcl_reproductible` directory even for steps that don't crash outright because it could still be that something goes wrong there.
For instan…
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```
INFO PSM-0064] Number of voltage sources = 88.
[WARNING PSM-0038] Unconnected PDN node on net vccd1 at location (367.200um, 1910.580um), layer: …
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### Prompt
The following list describes variables used by the flow but not documented. These variables could be potentially used by a user but I am still not confident whether this is the case for al…
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### Description
I noticed that `CLOCK_NET` is a required variable in the documentation. I never used it and I don't think it is utilized anywhere in the code
### Proposal
`CLOCK_NET` to be removed …
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This is pretty much a requirement for the `user_project_wrapper`.
In OpenLane 1 it would trigger a different yosys script but here, although the `Variable` exists, it doesn't do anything AFAICT.
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### Description
The power and ground straps are too close to the pins and prevent detailed routing from passing.
LEF writing takes forever (3 hours and still…