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Summary of proposal from #507:
Mainline Chisel 3:
- must declare ```val io = IO(...)```
- Blackboxes drop the ```io_``` prefix to all ports
- Modules keep the ```io_``` prefix to all ports
…
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Hello,
i followed the tutorial and succesfully compiled the verilator emulator with the PWM.
However running the emulator with the example code always leads to a segfault.
../emulator/emulator-…
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When I run make in the "verisim" directory, something goes wrong.
vicco@ubuntu:~/project-template/verisim$ make
cd /home/vicco/project-template/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=…
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Author Name: **Wesley Terpstra** (@terpstra)
Original Redmine Issue: 1165 from https://www.veripool.org
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In src/verilog.y there is this:
| yD_VALUEPLUSARGS '(' str ',' exp…
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I haven't had a chance to debug it, but the `RoccExampleConfig` isn't getting through FIRRTL:
For completeness, this is using 9c0cc6fdf480efa18a2a4119e6a6e0dfa9235e8e.
```
cd emulator
make CON…
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As a freshman, I follow the steps and make run in emulator.
It make finished without error and I get some .out files, but how can I make sure
the result is right?
Another problem, if I write a si…
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Hello,
I'm following your instructions for the zedboard. I have some questions related to the error below when building the host software:
```
alpha@alpha-VirtualBox:~/parallella-riscv$ ./scripts/…
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I try to use the `MegaBOOMConfig` in the `boom` branch of the `rocket-chip` repo, but it fails at the following requirement in `rocket/frontend.scala:126`
```
require(fetchWidth * coreInstBytes
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What should be the behavior of a declared register that is never assigned?
If I declare a register that is never assigned to anything [e.g. val ran_val_reg = Reg(Bool()) ], I would imagine that i…
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```[info] Set current project to rocketchip (in build file:/home/jsren/fpga-zynq2/rocket-chip/)
[info] Updating {file:/home/jsren/fpga-zynq2/rocket-chip/}coreMacros...
[info] Resolving edu.berkeley.…
jsren updated
7 years ago