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The formatter introduces whitespace around operators inside bit-selections. I'd argue these are better off as compact expressions, I note whitespace isn't added in declarations.
For example in http…
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This happens at least in CI (example: https://github.com/google/verible/pull/823/checks?check_run_id=2620255630#step:4:658 ):
```
$ verible-verilog-syntax.exe --version
Built 2021-05-19T12:49:01Z…
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STR: Run `vendor/lowrisc_ip/prim/rtl/prim_keccak.sv` (https://github.com/lowRISC/ibex/blob/master/vendor/lowrisc_ip/prim/rtl/prim_keccak.sv) through verible formatter.
Expected output, according …
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After fixing #556, the next issue is related to Kythe as a dependency.
See this log:
https://travis-ci.org/github/google/verible/jobs/742535455
```
INFO: Repository io_kythe instantiated at:
…
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Formatter input and output:
```systemverilog
task t;
if (r == t)
a.b(c);
endtask
```
The `a.b(c);` should either compact onto the same line as the `if` or be indented on its own line.
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### Problem description
After updating my config to the new recommended method (not using `on_server_ready`, I'm having issues with any language server installed by nvim-lsp-installer.
`…
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I was testing svlangserver with Emacs and lsp-mode and saw an error that was reported as an Info. I'm not sure if it's a problem with lsp-mode for Emacs, or svlangserver. The error/info occurs after r…
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As described in https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#basic-style-elements 6th bullet.
Example:
initial begin
case (x)
default : break;
1'b0 : b…
ghost updated
3 years ago
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Hi
I ran into a fatal error when trying to get svlangserver up and running on Emacs with lsp-mode. The error happens for all SystemVerilog files shortly after the file is opened in Emacs and lsp-mode…