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Are there any plans to support 32-bit words? I rewrote the division algorithm for a 32-bit machine and got an 18% speedup (testing was done on a [risc-v simulator](https://github.com/matter-labs/risc_…
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## Description
+ In upstream repo , the latest version is [openEuler-23.09-V1-riscv64](https://mirror.iscas.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/preview//openEuler-23.09-V1-riscv64)
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## Description
+ In upstream repo , the latest version is [openEuler-23.09-V1-riscv64](https://mirror.iscas.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/preview//openEuler-23.09-V1-riscv64)
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### Is your feature request related to a problem? Please describe.
We have the First Version of the NuttX Dashboard for our [Build Farm](https://github.com/lupyuen/nuttx-build-farm)!
Try it her…
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mvapich2-devel-2.3.6-3.oe2403.riscv64/usr/lib64/mvapich2/lib/libmpi.a
mvapich2-2.3.6-3.oe2403.riscv64/usr/lib64/mvapich2/lib/libmpi.so.12.1.1
mvapich2-2.3.6-3.oe2403.riscv64/usr/lib64/mvapich2/bin/m…
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**Describe the bug**
In the Nutshell design, when executing a load instruction with the destination register set to zero (e.g., c.ldsp zero, x(sp)) and the address is misaligned, a Load Address Mis…
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RISC-V failed like this:
https://github.com/DynamoRIO/dynamorio/actions/runs/5247579249/jobs/9477922603?pr=6137
```
[ 14%] Building CXX object clients/drcachesim/CMakeFiles/drmemtrace_func_view.dir…
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**Overview**
The RISC-V port of Go is currently restricted to the RV64G instruction set. It does not take advantage of any other RISC-V extensions that could be used to boost performance or reduce…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
### Summary
Hi all, we have found multiple compressed instructions that violate the [_…
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Suggest looking into if possible to replace ESP32-C3 SoC with ESP32-C6 in next-generation of WiCAN hardware for the future.
https://www.cnx-software.com/2023/01/12/esp32-c6-wifi-6-ble-802-15-4-modu…
Hedda updated
2 months ago