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Lets consider the following module :
```
(* synthesize *)
module mkModule#(parameter Bit#(0) _)(Reg(32);
...
endmodule
``…
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As reported by Dapeng Gao:
Trying to verify the CTestSubset instruction found the following counterexample, where the spec returns 0 but Flute returns 1:
# cs1
tag: 0
ad…
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Although it's undocumented, `bsc` does support SVA syntax/properties of the form:
```bluespec
import SVA::*;
module t(Empty);
let fooBool True;
endproperty
always assert property(te…
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Most bluespec errors can be demoted to warnings using the `-demote-errors` flag. One exception to this is G0006, which produces an error like the following
```
bsc -demote-errors G0006 -verilog Re…
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From personal communications, I heard that bluespec.com used to do their compiler builds in a Debian 3.1 VM with GHC 6.12 so that the resulting glibc and shared library dependencies were old enough th…
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Currently, bsc emits Verilog files that are named after modules defined within a source file, rather than the name of the source file. This complicates its use in build systems, which need to be able …
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The installation layout under `$PREFIX/lib` is a bit crowded and strange:
```
$ ls result/lib
Bluesim exec Libraries SAT tcllib Verilog Verilog.Quartus Verilog.Vivado VPI
```
This doe…
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Problems like https://www.xilinx.com/support/answers/70838.html might make SmartConnect still inferior to Interconnects. To avoid such problems (as well as performance problems we experienced e.g. on …
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Depending on how we comment an include :
```
//`include foo
// `include bar
```
the script for dependency tracking consider that foo is a dependency, but not bar. When I expect the two to not be…
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Right now, the following is not supported in connectal/scripts/bsvpreprocess.py (code from lib/BSVSource/Contexts/Contexts.defines within the Bluespec installation directory):
```
`define SynthBounda…