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cambridgehackers
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connectal
Connectal is a framework for software-driven hardware development.
MIT License
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obsolete bsc version checking bug in `scripts/Makefile.connectal.build`
#197
01xz
closed
1 year ago
2
Problem while building for zedboard
#196
Arch1610
closed
1 year ago
2
Support scoped enum bit width calculation
#195
GTwhy
closed
1 year ago
0
support the bitwidth calculation of decimal number scoped enumeration
#194
GTwhy
closed
1 year ago
5
fix buffer size
#193
GTwhy
closed
1 year ago
3
fix obsolete bsc version bug
#192
pwang7
closed
2 years ago
6
ERROR: could not insert 'portalmem'
#191
manish-pp
closed
2 years ago
2
error while running "make run.kc705g2"
#190
manish-pp
opened
2 years ago
9
Error while building for kc705, "recipe for target 'obj/Pcie1EndpointX7.bo' failed"
#189
manish-pp
closed
2 years ago
4
Error in pcieportal_ioctl function
#188
manish-pp
closed
2 years ago
5
Shuotao vcu118 rebased
#187
jameyhicks-cmt
closed
2 years ago
2
DataBusWidth=256 support
#186
RadhikaG
opened
3 years ago
8
PcieHost.bsv fails to build for multiple targets
#185
RadhikaG
closed
3 years ago
11
PCIe drivers fail to compile on Ubuntu 16.04
#184
CyanoKobalamyne
opened
3 years ago
3
Fix build fatal on RHEL8
#183
chenm001
closed
3 years ago
0
AWS: Allow projects to add additional files
#182
jrtc27
closed
3 years ago
0
Convert missed print statements and add future imports
#181
CyanoKobalamyne
closed
3 years ago
0
Python 3 compatibility mk. 2
#180
CyanoKobalamyne
closed
3 years ago
1
Python 3 compatibility
#179
CyanoKobalamyne
closed
3 years ago
0
Python 3 support
#178
CyanoKobalamyne
closed
3 years ago
4
Fix key when getting typedef
#177
CyanoKobalamyne
closed
3 years ago
0
AWS build script should check for credentials before starting the build
#176
jameyhicks
opened
4 years ago
0
Update XDMA drivers to latest upstream version
#175
jrtc27
closed
4 years ago
0
libxdma.c: Bug fix Xilinx/dma_ip_drivers#48
#174
jrtc27
closed
4 years ago
0
Replace XDMA driver with latest Xilinx upstream
#173
jrtc27
closed
4 years ago
0
Make bsvdependencies.py ignore wired outputs of bsc preprocessor
#172
kurocatus
closed
4 years ago
0
bsvdepend.py fails to find imported package whose name is expanded from macro
#171
kurocatus
closed
4 years ago
0
Fix bluesim compiling error when using open-source bsc
#170
kurocatus
closed
4 years ago
0
Is it possible to support the opensource bsc?
#169
kurocatus
closed
4 years ago
5
Don't flood syslog with a message on every interrupt
#168
jrtc27
closed
4 years ago
1
Allow projects to provide their own strategy overrides
#167
jrtc27
closed
4 years ago
0
Merge XDMA driver
#166
jrtc27
closed
4 years ago
0
Allow AWS F1 projects to configure their own clocks
#165
jrtc27
closed
4 years ago
0
AWS: Include Reset Bluespec Verilog library files
#164
jrtc27
closed
4 years ago
0
write documentation for bsvdepend.py
#163
jameyhicks
opened
4 years ago
0
Documentation embedded diagrams
#162
KoviRobi
opened
4 years ago
3
Update/fix README.md
#161
KoviRobi
closed
4 years ago
0
Simple Amazon AWS EC2 F1 example
#160
KoviRobi
closed
4 years ago
16
More #!/usr/bin/env python
#159
KoviRobi
closed
4 years ago
0
Bypass version mismatch problems in generated Makefile
#158
rajat-agarwal-
closed
4 years ago
1
Connectal Support for open source bsc compiler
#157
rajat-agarwal-
closed
4 years ago
10
Adding Connectal Support to DE5 Net Board
#156
NP95
opened
4 years ago
4
Added support for 2018 versions of the bluespec compiler
#155
acw1251
closed
5 years ago
0
Some fixes for synchronizing reset signals across clock domains
#154
acw1251
closed
6 years ago
0
Added unmanaged impl constraint option
#153
acw1251
closed
6 years ago
2
Use empty and full from all subfifos in mkDualClockBramFIFOF
#152
acw1251
closed
6 years ago
0
Removed PROJDIR variable from sdcard_spi Makefile
#151
acw1251
closed
6 years ago
0
300 Clocks pins of VCU108
#150
xushuotao
closed
6 years ago
0
Turn off DRAM B and D.
#149
sizhuo-zhang
closed
6 years ago
0
Fix version MIG controller, add minimal ddr example
#148
threonorm
closed
7 years ago
1
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