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cambridgehackers
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connectal
Connectal is a framework for software-driven hardware development.
MIT License
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Work in progress on DRAM for aws
#147
threonorm
closed
6 years ago
1
Change aws poller time: 10 times speed.
#146
threonorm
closed
6 years ago
4
pcieportal.c compile issue with Linux kernel 4.10
#145
demetriussuchkov
closed
4 years ago
5
pcieportal.ko issue
#144
hanw
closed
4 years ago
2
handle block comments that wrap lines
#143
acw1251
closed
7 years ago
0
bsvpreprocess.py hits AssertionError if backticks used in block comment
#142
acw1251
closed
7 years ago
13
Zynqmp SAXI_HP connection
#141
chanwooc
closed
7 years ago
0
Added SDIO pins for kc705g2 platform and sdcard_spi test
#140
acw1251
closed
7 years ago
0
mkPhysMemSlaveMux no longer forwards too much write data
#139
acw1251
closed
7 years ago
0
Removed default clocks from SyncAxisFifo32x8.bsv
#138
acw1251
closed
7 years ago
0
Added synth-ip.tcl to fastecho
#137
acw1251
closed
7 years ago
0
Added synth-ip.tcl for fastecho
#136
acw1251
closed
7 years ago
1
Added fastecho test to reproduce bug in issue #133
#135
acw1251
closed
7 years ago
0
Specify clock and reset for mkProbes in GetPutWithClocks.bsv
#134
acw1251
closed
7 years ago
0
FPGA indication dropped when lots of request/indication traffic?
#133
acw1251
closed
7 years ago
26
Parser for includes.
#132
threonorm
opened
7 years ago
6
fix dma_buf_export for kernel version 3.10.0
#131
tudang
closed
7 years ago
2
dual_clock fifo and bsvpreprocess.py
#130
hanw
closed
7 years ago
3
Errors while compiling nvme_test
#129
pietrobressana
closed
7 years ago
1
LOC -> PACKAGE_PIN in generate_constraint.py
#128
hanw
closed
7 years ago
1
DDR3 Test doesn't do anything
#127
tudang
opened
7 years ago
37
Close forgotten files. Add quick and dirty bsv packaging script.
#126
threonorm
closed
8 years ago
0
Make a module bsvdependencies. Use it to generate the makefile.
#125
threonorm
closed
8 years ago
1
build error with netfpga sume
#124
tudang
closed
8 years ago
8
Remove -O1 from C_RULE and CXX_RULE.
#123
hanw
closed
8 years ago
0
fixed bug in topgen.py with multiple portalReaders and portalWriters
#122
acw1251
closed
8 years ago
3
Support Third-Party simulate (verify on ncverilog and vcs only)
#121
chenm001
closed
4 years ago
9
Issue with portalCacheFlush in memcpy example?
#120
psrawke
opened
8 years ago
9
'memcpy' example: program does not end
#119
psrawke
closed
8 years ago
12
Added BSVPATH to makefilegen.py call and added deriving FShow to some types
#118
acw1251
closed
8 years ago
1
add all files in bsvpath to abspaths for path lookup
#117
acw1251
closed
8 years ago
1
__STDC_FORMAT_MACROS only defined if not already defined
#116
acw1251
closed
8 years ago
1
Issues with defined macros in bsvpreprocessor.py
#115
acw1251
opened
8 years ago
3
axiddr3, dma, vsim, generate_constraint.py
#114
hanw
closed
8 years ago
2
From AXI spec, VALID signals should not depend on READY signals.
#113
chanwooc
closed
8 years ago
1
support for NetFPGA Sume
#112
tudang
closed
8 years ago
13
some updates for new zynq kernel
#111
chanwooc
closed
8 years ago
1
fixed-make-install-dependences
#110
tudang
closed
8 years ago
7
touched nfsume support, altera pcie and vsim
#109
hanw
closed
8 years ago
1
misc changes
#108
hanw
closed
8 years ago
0
Support thirdpart simulate
#107
chenm001
closed
8 years ago
1
build error on x86, file dmaSendFd.h, line 85
#106
chenm001
opened
8 years ago
8
removed source_msim_setup.py, load simulation library with -y and -v
#105
hanw
closed
8 years ago
0
support for Avalon Memory-mapped slave, with tests/avalon_mm example
#104
hanw
closed
8 years ago
2
fixing poller seg_faults and deadlock, by KiSuh
#103
hanw
closed
8 years ago
3
remove explicit clock & reset in AvalonBFM.bsv
#102
hanw
closed
8 years ago
0
use bfm in modelsim simulation
#101
hanw
closed
8 years ago
1
invoke vsim inside portal.c
#100
hanw
closed
8 years ago
1
modelsim supports portal now, and first cut on altera ddr3 controller.
#99
hanw
closed
8 years ago
0
drop support for xilinx pcie gen1
#98
jameyhicks
opened
8 years ago
0
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