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cambridgehackers
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connectal
Connectal is a framework for software-driven hardware development.
MIT License
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make[1]: *** No rule to make target `/home/jamey/connectal/bsv/Ddr3Controller.bsv', needed by `obj/Makefile'. Stop.
#97
jameyhicks
closed
8 years ago
1
warning: overriding commands for target `verilog/mkPcieEndpointX7.v'
#96
jameyhicks
opened
8 years ago
0
PhysMemToBram with ByteEnable
#95
hanw
closed
8 years ago
1
minor fixes for adding Page12 support
#94
hanw
closed
9 years ago
0
Added Page12 and Memwrite128 example
#93
hanw
closed
9 years ago
4
Altera: bugfix on avalon alignment for DMA Read
#92
hanw
closed
9 years ago
1
PcieTracer: changed FIFO1 to FIFO
#91
hanw
closed
9 years ago
0
DMA read works for Altera, if not using traceif
#90
hanw
closed
9 years ago
0
Altera: MemSlaveEngine works for MWr64
#89
hanw
closed
9 years ago
1
MemSlaveEngine works for Altera if DMA to 32bit address
#88
hanw
closed
9 years ago
1
altera: does not support partitions yet, fixed compilation error
#87
hanw
closed
9 years ago
0
path fix for altera constraint file generation
#86
hanw
closed
9 years ago
0
NFSume PCIe Gen3: works at gen2 speed and Echo works.
#85
hanw
closed
9 years ago
0
suppressed warning
#84
hanw
closed
9 years ago
1
added axi interface in pcigen3
#83
hanw
closed
9 years ago
1
bugfix and simplified PCIEWAPPER3.bsv
#82
hanw
closed
9 years ago
1
fixed location of pcie gen3 core and pin assignments
#81
hanw
closed
9 years ago
1
added bram1.v to verilog/altera
#80
hanw
closed
9 years ago
1
xilinx gen3 passes example simulation configuration stage
#79
hanw
closed
9 years ago
1
skip altera coregen if we don't have quartus_sh
#78
hanw
closed
9 years ago
1
misc fixes.
#77
hanw
closed
9 years ago
0
Fixed PLL Settings for DE5
#76
hanw
closed
9 years ago
0
fixed altera pcie MSI-X settings
#75
hanw
closed
9 years ago
0
Interrupt working!
#74
hanw
closed
9 years ago
0
fixed PIN_BINDINGS for altera constraints generation script
#73
hanw
closed
9 years ago
0
bump pcieportal to 15.04.3
#72
hanw
closed
9 years ago
0
fixed pcieportal free_irq bug
#71
hanw
closed
9 years ago
1
fixing sdc names and pcieclock
#70
hanw
closed
9 years ago
0
changes to compile 10G Ethernet on sonic-lite
#69
hanw
closed
9 years ago
0
removed Mac wrapper
#68
hanw
closed
9 years ago
0
remove leds subinterface from ConnectalTop
#67
jankcorn
closed
9 years ago
1
autoload bitfile when app program starts up
#66
jankcorn
closed
9 years ago
2
bugfix: path for generated qsf.
#65
hanw
closed
9 years ago
0
pcie, ioread32 and cleanup.
#64
hanw
closed
9 years ago
0
Modelsim Simulation for Altera PCIE
#63
hanw
closed
9 years ago
1
support multi-FPGA models in bluesim
#62
jameyhicks
closed
9 years ago
2
Update dma2bram to use topgen.py
#61
hanw
closed
9 years ago
0
connectal/doc/library/source/design/portal.rst
#60
hanw
opened
9 years ago
0
Simulate DataBusWidth=256 in Bsim
#59
hanw
closed
9 years ago
2
Support 256-bit DataBusWidth in PCIe
#58
hanw
opened
9 years ago
2
remove vim as build dependency for zedboard
#57
jankcorn
closed
9 years ago
2
clean up python support (use json serialization)
#56
jankcorn
closed
8 years ago
0
generate xilinx pin constraints from .pkg file
#55
jameyhicks
opened
9 years ago
5
DMA burst size limited to 32
#54
hanw
closed
9 years ago
6
add python-netifaces as a dependence
#53
jameyhicks
closed
9 years ago
5
support ac701
#52
jankcorn
opened
9 years ago
0
support routing portal packets to connected fpga devices
#51
jankcorn
opened
9 years ago
1
support generic tracing facility for debug
#50
jankcorn
opened
9 years ago
0
support sockit
#49
jankcorn
opened
9 years ago
0
support zybo
#48
jankcorn
closed
9 years ago
1
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