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cambridgehackers
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connectal
Connectal is a framework for software-driven hardware development.
MIT License
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fix pcie on new hardware
#47
jankcorn
closed
8 years ago
2
portals over aurora
#46
jankcorn
opened
9 years ago
0
portals over jtag
#45
jankcorn
opened
9 years ago
0
update AXI trace dump
#44
jankcorn
opened
9 years ago
0
fpga config readback/decode
#43
jankcorn
opened
9 years ago
0
update printf support with shared memory i/f
#42
jankcorn
opened
9 years ago
0
packet interface option for bsim
#41
jankcorn
opened
9 years ago
0
virtualbox for testing kernel modules w/bsim
#40
jankcorn
closed
8 years ago
1
repair bscan
#39
jankcorn
opened
9 years ago
0
cleanup imageon
#38
jankcorn
closed
8 years ago
0
importbvi for xilinx pcie
#37
jankcorn
closed
8 years ago
1
AUTOTOP mkBluenocTop
#36
jameyhicks
closed
9 years ago
1
clean up with pcie code
#35
hanw
closed
9 years ago
0
clean up with pcie code
#34
hanw
closed
9 years ago
0
de5 constraints
#33
hanw
closed
9 years ago
1
bugfix: transceiver block generation.
#32
hanw
closed
9 years ago
0
bugfixes
#31
hanw
closed
9 years ago
0
Pcie Gen2 x8 boots
#30
hanw
closed
9 years ago
0
removed --qsf options, use --tcl option instead
#29
hanw
closed
9 years ago
0
makefilegen.py
#28
hanw
closed
9 years ago
0
Json and PLL wrapper
#27
hanw
closed
9 years ago
0
Parse QSF to JSON
#26
hanw
closed
9 years ago
0
Added support for signaltap II and fix for simulation.
#25
hanw
closed
9 years ago
0
Debug pcie
#24
hanw
closed
9 years ago
0
Debugging Pcie
#23
hanw
closed
9 years ago
0
bugfix: correct port type for /*AUTOARG*/ generated ports
#22
hanw
closed
9 years ago
0
update ETH PMA and MAC wrappers
#21
hanw
closed
9 years ago
0
moved B2C and C2B to ConnectalClock.bsv
#20
hanw
closed
9 years ago
1
bugfix: wrong module name, should be mkBsimPcieTop
#19
hanw
closed
9 years ago
0
Fixed support for /*AUTOARG*/ generated port names.
#18
hanw
closed
9 years ago
0
Three commits in the same pull request, as I don't know how to separate them in github
#17
hanw
closed
9 years ago
1
Fix: top-level signals and pin assignments
#16
hanw
closed
9 years ago
1
Add Verilog.Quartus to search path and use it when appropriate.
#15
hanw
closed
9 years ago
0
First end-to-end compilation of Altera flow for 'simple' example
#14
hanw
closed
9 years ago
3
Added PcieEndpoingS5.bsv
#13
hanw
closed
9 years ago
0
Added miscellaneous support elements for PCIe design
#12
hanw
closed
9 years ago
0
Added Altera Pcie Simuation
#11
hanw
closed
9 years ago
0
Wrapped PcieEndpointS5 with reconfiguration controller
#10
hanw
closed
9 years ago
0
WIP: altera pcie wrapper
#9
hanw
closed
9 years ago
0
Updated address hashing so we don't exceed flash model boundaries
#8
m-liu
closed
9 years ago
0
test case for strstr and flash model
#7
m-liu
closed
9 years ago
0
Changed flash addr width to 43; pending fix
#6
m-liu
closed
9 years ago
0
Added page buffers for flash MemSlave ifc; FIXME: PhysAddrWidth=43 does ...
#5
m-liu
closed
9 years ago
0
flash top fixes
#4
m-liu
closed
9 years ago
0
flash stuff
#3
m-liu
closed
9 years ago
0
Added sw to access flash
#2
m-liu
closed
9 years ago
0
Connected flash model with strStr. Compiles BSIM, untested
#1
m-liu
closed
9 years ago
0
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