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It would be great to have fault generate the relative ordering between all the edges for multiple clocks.
In terms of API, I think something along the lines of:
```
tester = fault.Tester(circ,c…
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When using the clock-gated registers output by CoreIR, the synthesis tools do not recognize this and put a correctly clock-gated register cell in the design. @mbstrange2 has more details.
In the me…
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https://github.com/rdaly525/coreir/blob/master/src/ir/moduledef.cpp#L114-L132
Should check if prev or next are nullptr before updating the map. Also clarify the logic on the case that the instance …
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```
import magma as m
import mantle
# Workaround
def make_LUT(*args, **kwargs):
for i in range(1000):
try:
return mantle.LUT(*args, **kwargs)
except Exception…
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```python
import magma as m
class Foo(m.Circuit):
IO = ["IFC", m.Tuple(I=m.In(m.Bit), O=m.Out(m.Bit))]
@classmethod
def definition(io):
pass
if __name__ == "__main…
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Currently the verilog for commonlib.MuxN is generated like the following:
```
module commonlib_muxn__N2__width9 (
input [8:0] in_data [1:0],
input [0:0] in_sel,
output [8:0] out
);…
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The verilog logic relies on unsafe information like 'primitive_type' ('unary', 'binary', 'mux', 'other') that were originally just a way to efficiently generate verilog primitives. This should be chan…
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You should be able to emulate verilog code written like the following:
```
module foo(...)
wire a_to_b;
wire [15:0] b_to_a;
A my_a_inst(
.bar(a_to_j),
.baz(b_to_a)
);
B my_b_inst(…
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@jeffsetter @rdaly525 I'm guessing this is related to #108 but there is an error in one of the Harris sch4 compute units:
```bash
ERROR in compute unit: hcompute_cim_stencil
in0_lgxx_stencil[0] -…