-
More of a question than an issue, so please bear with me.
I got into FPGAs from the MiSTer project, and was intrigued to see how large the (G2) Pano Logic’s FPGA is, even though it doesn’t have a c…
-
Is the DeepCL can only run on GPU or APU? Could it run on FPGAs? Such as altera?
-
Hello and thank you for writing!
In general, supporting a different development board is not too complex, but there are three requirements:
1. The FPGA (programming logic) must have direct access …
-
git clone https://github.com/micropython/micropython.git
cd micropython/ports
cp -avr /micropython/ztachip_port .
cd ztachip_port
export PATH=/opt/riscv/bin:$PATH
export ZTACHIP=
make clean
mak…
-
Hi, I'm trying to synthesize this project and running into some errors.
I have very little experience with FPGAs so I'm sure I'm doing something wrong. I'm willing to learn though. My goal is to cr…
-
When the Digilent Atlys is still running the firmware which ships with the board (supplied by Digilent) the SPI flash is automatically configured in QSPI mode which openocd doesn't know how to talk.
…
-
Currently if you wish to only build a core file to a particular stage (setup, build, run) you can only do so through the CLI, using the equivalent arguments.
I propose adding a "stage" element to a…
-
Hi,
I struggled with this strange issue for a couple of days and finally found out that,
for some weird reason, configuration failed (DONE pin on the FPGA not coming high)
when I tried to load a L…
-
Estimados Amigos:
Hace 2 días finalmente llegó mi placa Cariboulite, y estoy muy contento de haberla recibido, pero no logro hacerla funcionar.
La tengo instalada en una Raspberry PI Zero, y he …
-
The G2 I tested with is an LX100 variant, and during flash readback or programming, it drops Vref on the JTAG thus the programming fail. Has programming of the LX100 Pano with standard 14.7 and DLCP9 …