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Hi,
I am using Quartus Prime Lite 18.1 with FuseSoC on Windows 10.
I have installed gnu make for windows.
When running "fusesoc --cores-root=. run --target=...", a makefile is generated.
The scr…
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Is it possible to extract the control signals of the processor corresponding to the RTL code of the or1200 processsor for a given set of instructions ?
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While building simulation from Ibex Repo folder, I got this error.
_sh-5.0$ fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
ERROR: 'lowrisc:ibex:d…
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Hello everyone, I was attempting to install fuseSOC in my windows 11. The download and installation went well until I ran the "fusesoc --version" command. It says that ...
> 'fusesoc' is not recogn…
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This issue is a discussion thread and followup about adding Chisel support to TerosHDL extension.
Here I list the initial points I identify as requirement for support:
- Chisel is a DSL based on…
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ok, there are a bunch of wonkiness things going on here (WSL, I know I have python 3.x installed, etc.)
But perhaps `pip install fusesoc` could detect problems and return a more friendly message?
…
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I encountered a ValueError exceptions if the fusesoc project is located on a drive that isn't the C: drive and a generator is called that creates a .core file, or a used library is located on another …
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The [Yosys GHDL plugin](https://github.com/ghdl/ghdl-yosys-plugin) is still listed as experimental but is already very useful. For formal verification GHDL's support for PSL seems more extensive than …
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**Brief introduction of the Arrow Chameleon96 board (https://www.96boards.org/product/chameleon96/):
This board is a Cyclone V board (same chip as de10-nano) but FPGA was considered secondary and Nov…
somhi updated
3 years ago
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I would love to integrate Icestudio as a generator in FuseSoC so that the .ice files can be converted to verilog as part of the build flow. This would require calling icestudio in batch mode to do the…
olofk updated
4 years ago