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Verification has failed on main branch:
```
$ make test
iverilog -o test.out src/*.v tests/programcounter_tb.v; vvp ./test.out; rm test.out
src/controller.v:327: warning: Extra digits given for …
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### What's hard to do? (limit 100 words)
Due to the lack of interactive DSLX debugger when troubleshooting a logic issue in a `fn` developers can't really introspect value of intermediate let bindi…
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Hello, we found a potential Iverilog warning information oversight error.During the analysis of the program, we found that there is a potential issue with the synthesis of “module141” where the width …
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Accessing parameters by upward-looking hierarchical name seems to always return the value as specified in alphabetically first(!) instance of the module in question.
This is tested with the vlog95 …
hpax updated
6 months ago
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I am using IceStudio version below on Mac OSX Sonoma 14.3 (couldn't not copy it as text for some reason).
The iverilog and vvp binaries are already included with the IceStudio installation but …
zapta updated
6 months ago
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It seems iverilog does not yet support load tracing in its vpi implementation (no vpiDriver/vpiLocalDriver/vpiLoad/vpiLocalLoad defined).
Are there an alternative way to do this in iverilog or is t…
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> **Describe the bug**
OpenFPGA fabric verilog configured with a bitstream has undefined outputs. This is true even for the and2 basic example provided in the template tasks/fabric_verification_templ…
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Compiling Verilator for each CI run is very inefficient, because it takes around 15 Mins. It would be nice to have a docker container that contains all the necessary software (Verilator, iverilog, coc…
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It seems that some of the package are not compatible with the runtime environment present in https://colab.research.google.com/.
Installing the following packages with:
```
!curl -O https://repo…
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Hi,
The traditional way to build icarus verilog for Windows seems to be using Msys. I didn't want to embark on this (sometimes complicated) path, and as a fun experiment I decided to build on linu…