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Hi,
Thanks for your efforts.
I wanted to run a simulation as mentioned in http://sergeykhbr.github.io/riscv_vhdl/verification_page.html#sim_tb_link and unable to find the mentioned testbench file …
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Hello,
Thanks for this great work, I appreciate the whole work. It is extremely beneficial.
Actually,I removed the constraint file of KC705 board, and I used the constraint file of VC707 board, and …
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I am using kc705 and fmcdaq2. Can I be able to see the dac output in IIO scope . If so, does it require any additional modules in the design?
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# Bug Report
## One-Line Summary
Artiq hardware signal output/dashboard updates freeze/drop out for about 5 seconds every 30 seconds when RPC is used.
## Issue Details
MWE (after T…
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I am new to FPGA. I'm sorry if the question is simple. I'm not even sure how to ask a question on FPGA.But it really bothered me for a long time.
I have a DIGILENT development board Genesys2 and AD91…
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I found that the kintex7'dbs exist in prjxray-db,however symbiflow's cmakelist didn't use kintex7? whether the reason is the loss of primitives in some IP source such as iob18(in the dir of xc/common/…
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hi
When i execute the next cmd
make update-submodules
it stop at the followling log
Cloning into '/home/e665106/Downloads/vivado-risc-v/linux-stable'...
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hi bro KC705 Can it work?
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I kindly ask you to update fpga for sp605 because kc705 I am still trying to modify Thank you very much otherwise there is no way I can continue working on this work Thank you very much for your proje…