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traceSignals function incorrectly writes real value signal to VCD. Verilog Standard states that a real value signal in VCD dump should start with "r" or "R" identifier. But instead, MyHDL creates sign…
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Summary
When trying to introduce a shift left code, where I want to initialize a value by shift the number 1 into a vector:
full_length = 16
q = Signal(modbv(0)[full_length:])
…
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* Verilog Main still doesn't work. Possibly hierarch design to figure out where the issue is. converting project to 0.10 style fully may help with this as well.
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I propose that the next version of MyHDL should be 0.10
There are no backwards incompatible features yet. Using the legacy conversion and simulation functions produce warnings. Users can incrementa…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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Hi,
the request is to support the slice type (for Python2 and Python3, if possible)
```
MySlice=slice(3,0)
from myhdl import *
@block
def inc(Sin, Sout):
@always_comb
def com…
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During conversion detect when a ShadowSignal is attempting to be used inside a MyHDL generator (the generator being converted). For new users this can be a source of confusion because there are to me…
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Hi All,
It appears slicing (shadow signals) does not work if there are multiple interface objects.
For the example below, the line "if a_slice == 3" is getting translated into verilog as "if (0 ==…
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This is intended to be a feature enhancement request (MEP lite).
A common issue experienced by many new MyHDL users is how constants are converted. More commonly than not, these constants are contai…
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I had one more error in my conversion of a MyHDL module. I wrote a small test-module to isolate it, and found a work-around, but the same issue also appeared in another place.
This code:
``` python
'…
josyb updated
7 years ago