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Including the file [bsg_dff_chain.sv](https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_dff_chain.sv) from BaseJump STL in a Lakeroad integration test can cause it to fail…
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1. Add `stop(code: UInt): Unit`. I am not sure whether it is possible. It could be more useful if `stop` can pass the internal circuit state outside.
2. Add `finish()`, finish has different meanings …
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Modern standard cell libraries include flops with asynchronous sets. For example, DC maps
```
module f(
input clk_i,
input rst_ni,
input set_i,
input q_i,
output reg q_o…
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I'm using Vunit with verilog/systemverilog and xcelium
I have a strange issue. When in my setup I use multiple thread with the option:
python run.py --num-threads 5
Some tests are randomly fail…
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# Target
- Become familiar with HW RTL design with CPU design orientation by designing a simple CPU in SystemVerilog.
# Background
- The MAFIA Project is a HW/SW co-design platform for the deve…
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Hi,
I'm a Computer Science Engineering student in Spain and I'm using RIPES for my final degree's project. My aim is to add a new processor model, which is described in System Verilog.
I am follow…
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We want a structured way to write unit tests for the sim.v files (and a way to run them).
We want the unit tests to be compatible with at a minimum;
* Yosys
* Verilator
* Icarus Verilog
Bu…
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Using the information below create a LEMA tutorial:
1)Type LEMA to bring up LEMA gui.
2)File -> New -> Project (Enter name)
3)File -> New -> Labeled Petri Net (Enter name, say one). After this,
you…
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Hi,
I've been trying to use `sqrtFP` from the `FloatingPoint` library, and I was getting incorrect results. I then ran `make check` in `testsuite/bsc.lib/FloatingPoint` (with `testArith = True`) an…
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I'm using cocotb in amongst a bunch of UVM and legacy verilog testbenches. The VPI layer is linked in for all the builds, along with various other VPI models. Right now, if CocoTb starts and isn't han…