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Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails:
`fusesoc sim mor1kx-generic --elf-load hello.elf`
I g…
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http://www.elecfans.com/emb/fpga/20170210483296.html
http://xilinx.eetrend.com/blog/2022/100561106.html
7系列FPGA是Xilinx新推出的基于28nm工艺的FPGA,其中包含三个系列:ArTIx、Kintex和Virtex。因项目要使用kintex7为平台做设计,需要对其内部结构做了研…
cisen updated
2 years ago
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Hello,
I'm setting up a new NetFPGA board following the guide [here](https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Getting-Started-Guide). I'm using Ubuntu 20.04.3 LTS and with the …
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I'm running the binary cross-compiled from `modules/libcom/test/epicsTimeTest.cpp` from EPICS 7.0.6.1 built using gcc 4.7.2 (arm-xilinx-linux-gnueabi target).
These are the test results from my arm…
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Hello All,
I have a **xilinx ZCU102 board.**
I just have two questions:
1. This project is pretty old. Has there been no update in bitcoin code in last 11 years? I am asking because ethereu…
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Hi,
I'm using fusesoc+edalize for synthesis on zynq mpsoc platform.
Now I would like to also simulate some of my subdesigns with xsim (or any other simulator for that matter), which is not a stra…
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The new USB support is nominally working, but I'm getting a lot of random 'usb_bulk_*' messages. Worse, I cannot transcribe them because my monitor is constantly displaying "Analog Input" at the uppe…
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Hello,
I've successfully synthetized the whole VHDL code to fit a spartan-6 and simulated it with Xilinx tools.
Now I would like to put my own sketch in the softcore program memory.
But to start wi…
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**Description**
It seems that if only a part of the record being an output of the entity is driven, GHDL does not drive the whole record.
**Expected behaviour**
The undriven part of the record sh…
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I just left PR #1 to start this effort.
My ultimate target (I would love to hear your feedback) is to be able to reuse old ESP8266-01 for JTAG programming via WiFi. I don't want to store any bitstrea…