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There is currently no simd_op_check coverage for RISC V vector. This should be added. It will require adding some test setup to the buildbot configuration.
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First, a simple clarification: the spec says
> it is expected the high-level RoT / boot flow requirements
What is "RoT" in this context? I'm not familiar with the acronym and it's not defined i…
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In RISC-V "V" Vector Extension Version 1.0 chapter 15.1, instruction `vmandnot` and `vmornot` have been changed to `vmandn` and `vmorn`.
But in the `riscv/arch_data/v_instructions.xml`, the instructi…
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ML2CPP can generate specific C++ code with RISC-V extensions allowing all scikit-learn, pytorch, caret ML models to be deployable natively on this platform.
RISC-V extensions have the advantage t…
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When trying to build aktualizr 2019.9 for QEMU RISC-V 64:
```
/home/rsalveti/build/lmp/build-lmp/tmp-lmp/work/riscv64-lmp-linux/aktualizr/1.0+gitAUTOINC+a358242d9a-7/recipe-sysroot-native/usr/bin
…
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## 说明
问题背景: electron 可选 HdrHistogram_c
涉及软件包: HdrHistogram_c
涉及软件包地址: https://github.com/HdrHistogram/HdrHistogram_c
所需技能:
其它: 需要引入到 src-openeuler，但这个包不需要放置到 RISC-V sig 下管理。
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Ubuntu 24.04.1 LTS on x86_64, LLVM 20.0.0git with riscv-gnu-toolchain installed at /opt/riscv_2
The following problem occurs while cross compiling [ggml.c](https://github.com/ggerganov/llama.cpp/b…
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How many vector lanes does this Gem5 for RISC-V Vector support? Is it possible to change vector lanes at this point?
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**Describe the problem you have/What new integration you would like**
Please consider adding platform support for the new RP2350 MCU and their official Raspberry Pi Pico 2 development board. …
Hedda updated
3 months ago
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I'm simulating a big project related with RISC-V and one problem was found. The V3VariableOrder takes tow much memory and compile time. After the V3Common::commonAll() is finished, verilator takes ab…