-
I was wondering if this project could be used as a replacement for the Ethernet subsystem provided by Xilinx in Vivado. The Subsystem holds a MAC, Ethernet Buffer and PCS/PMA module. The MAC is not fr…
-
#critical
Hi,
We followed all the steps for RISC-V setup on PYNQ Z2 board. But during the last step, in packaging the overlay, when we tried to run this code
`import numpy as np
arg1 = np.a…
-
~~One useful capability would be to automatically add a buffer cell (LUT1 or FDRE) similar to the way "update_design -buffer_ports" operates in Vivado. This would help with integrating multiple desig…
-
## CVE-2023-1989 - High Severity Vulnerability
Vulnerable Library - linux-xlnxxilinx-v2019.2
The official Linux kernel from Xilinx
Library home page: https://github.com/Xilinx/linux-xlnx.git
Found …
-
## CVE-2018-18710 - Medium Severity Vulnerability
Vulnerable Library - linux-xlnxxilinx-v2019.2
The official Linux kernel from Xilinx
Library home page: https://github.com/Xilinx/linux-xlnx.git
Fou…
-
## CVE-2021-28972 - Medium Severity Vulnerability
Vulnerable Library - linux-xlnxxilinx-v2019.2
The official Linux kernel from Xilinx
Library home page: https://github.com/Xilinx/linux-xlnx.git
Fou…
-
## CVE-2020-13974 - High Severity Vulnerability
Vulnerable Library - linux-xlnxxilinx-v2019.2
The official Linux kernel from Xilinx
Library home page: https://github.com/Xilinx/linux-xlnx.git
Found…
-
This will save a lot of time during debugging. We can use some ready-to-use core:
- https://opencores.org/projects/jtag
- https://www.xilinx.com/products/intellectual-property/bscan-to-jtag-convert…
-
Hi,
the current ARM GIC implementation ignores writes to the IGROUP register if the GIC is a revision 1 GIC. This is not the correct behaviour as a revision 1 GIC with TrustZone extension does have t…
-
src/com/xilinx/rapidwright/gui/ModuleInstanceScene.java creates a pixel image of a Module Instance at the current location, then moves that image to all possible location to visualize them.
Some mo…