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### Description
This bug was found by @anall. This reduced test case shows the issue:
https://github.com/anall/bug-openlane_hang/tree/reduced
OpenLane hangs at step 12 trying to print clock s…
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### Description
`-from` and `-to` support is dropped under a big umbrella of dropping support to continue the flow from an existing run. With that, there is no need to have non-overwrite behavior.
…
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## Description
Hi, I am installing OpenLane on Ubuntu 20.04 but I get this error:
```
Traceback (most recent call last):
File "./venv/bin/volare", line 8, in
sys.exit(cli())
File …
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Hi, thank you for your work. I have an issue regarding the format prediction part during evaluation for val/test in [openlane_v2_dataset.py#L386](https://github.com/OpenDriveLab/OpenLane-V2/blob/ddfcc…
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### Description
[STEP 10]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/openlane/user_proj_example/runs/22_12_05_08_…
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Please create a script generate a summary for timing using openSTA scripts for users.
Report should also provide a clear pass / fail status.
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OpenLane 2 currently does not have verified functionality with GF180.
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### Description
Hi, I am new to OpenLane and have been following the MPW-6 Walkthrough tutorial using the same RTL files in the walkthrough example. However, I am encountering the warning below when …
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In the following section, in `picorv32.v`:
```
for (i = 0; i < 32; i = i + 1) begin
assign gpio_all_dat_o[i] = |(gpio_dat_o[i][`OPENFRAME_IO_PADS-1:0]);
end
```
``[`OPENFRAME_IO_PADS-1:…
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INTENTION: to set path groups, so we need list of inputs ,registers and outputs from sta tool after reading sythesised verilog.
now,after reading liberty,verilog and linking the design ,all_inputs,…